How to Implement Clock Gating in Verilog: Syntax and Example

To implement clock gating in Verilog, use an enable signal to control a clock gating cell or a clock enable signal that gates the clock input to flip-flops. This reduces power by stopping the clock when the circuit is idle, typically done by ANDing the clock with an enable signal inside a module.

Syntax

Clock gating in Verilog is usually done by creating a gated clock signal using an enable signal. The common pattern is to AND the original clock with an enable signal to produce a gated clock.

Example parts:

• clk: Original clock signal.
• enable: Signal that controls when the clock is active.
• gated_clk: Resulting clock after gating.

verilog

wire gated_clk;
assign gated_clk = clk & enable;

Example

This example shows a simple clock gating implementation where a flip-flop only toggles when enable is high. The gated clock is generated by ANDing the clock with the enable signal.

verilog

module clock_gating_example(
    input wire clk,
    input wire reset,
    input wire enable,
    input wire d,
    output reg q
);

wire gated_clk;
assign gated_clk = clk & enable; // Clock gating

always @(posedge gated_clk or posedge reset) begin
    if (reset)
        q <= 0;
    else
        q <= d;
end

endmodule

Common Pitfalls

Common mistakes when implementing clock gating include:

• Generating glitches: Directly ANDing clock and enable can cause glitches on the gated clock, leading to unreliable behavior.
• Timing issues: Gated clocks can cause timing problems and make timing analysis harder.
• Using gated clocks in multiple places: It is better to use clock enable signals inside flip-flops rather than gating the clock externally.

Better practice is to use clock enable signals inside synchronous blocks instead of gating the clock signal directly.

verilog

/* Wrong way: direct clock gating can cause glitches */
assign gated_clk = clk & enable;

/* Better way: use clock enable inside always block */
always @(posedge clk or posedge reset) begin
    if (reset)
        q <= 0;
    else if (enable)
        q <= d;
end

Quick Reference

Concept	Description
Clock Gating	Stopping clock signal to save power when not needed.
Enable Signal	Controls when clock is active or flip-flop updates.
Gated Clock	Clock signal ANDed with enable (may cause glitches).
Clock Enable	Preferred method: enable signal inside flip-flop logic.
Glitches	Avoid direct gating to prevent unstable clock edges.

Key Takeaways

Use an enable signal to control clock gating and reduce power consumption.

Directly gating clocks with AND can cause glitches and timing issues.

Prefer using clock enable signals inside flip-flops rather than gating clocks externally.

Always reset flip-flops properly when using gated clocks or enables.

Test clock gating logic carefully to avoid unreliable circuit behavior.