Verilog Code for Frequency Divider by 3: Simple Example

A frequency divider by 3 in Verilog can be implemented using a counter that counts from 0 to 2 and toggles the output clock every time the count resets. Use a reg counter and a reg output clock signal inside an always block triggered by the input clock's rising edge.

Syntax

The frequency divider by 3 uses a counter that increments on each rising edge of the input clock. When the counter reaches 2, it resets to 0 and toggles the output clock signal. This creates an output clock with one-third the frequency of the input.

• reg [1:0] count;: 2-bit register to count 0,1,2.
• reg clk_out;: output clock signal toggled every 3 input clocks.
• always @(posedge clk_in or posedge reset): block triggered on input clock or reset.

verilog

module freq_div_by_3(
    input wire clk_in,
    input wire reset,
    output reg clk_out
);

    reg [1:0] count = 0;

    always @(posedge clk_in or posedge reset) begin
        if (reset) begin
            count <= 0;
            clk_out <= 0;
        end else begin
            if (count == 2) begin
                count <= 0;
                clk_out <= ~clk_out;
            end else begin
                count <= count + 1;
            end
        end
    end

endmodule

Example

This example shows a complete Verilog module that divides the input clock frequency by 3. The output clock toggles every 3 input clock cycles, effectively reducing the frequency to one third.

verilog

module freq_div_by_3(
    input wire clk_in,
    input wire reset,
    output reg clk_out
);

    reg [1:0] count = 0;

    always @(posedge clk_in or posedge reset) begin
        if (reset) begin
            count <= 0;
            clk_out <= 0;
        end else begin
            if (count == 2) begin
                count <= 0;
                clk_out <= ~clk_out;
            end else begin
                count <= count + 1;
            end
        end
    end

endmodule

// Testbench to simulate the frequency divider
module testbench();
    reg clk_in = 0;
    reg reset = 1;
    wire clk_out;

    freq_div_by_3 uut(
        .clk_in(clk_in),
        .reset(reset),
        .clk_out(clk_out)
    );

    // Generate input clock with period 10 time units
    always #5 clk_in = ~clk_in;

    initial begin
        $dumpfile("freq_div_by_3.vcd");
        $dumpvars(0, testbench);
        #12 reset = 0; // Release reset after some time
        #100 $finish;
    end
endmodule

Output

Simulation waveform shows clk_out toggling every 3 clk_in cycles, dividing frequency by 3.

Common Pitfalls

Common mistakes when creating a frequency divider by 3 include:

• Using a simple toggle on every clock edge without counting, which divides frequency by 2, not 3.
• Not resetting the counter properly, causing unpredictable output.
• Using a 1-bit counter which cannot count to 3.

Always use a 2-bit counter and toggle output only when count reaches 2.

verilog

/* Wrong approach: toggling output every clock edge divides by 2 only */
module wrong_div_by_3(
    input wire clk_in,
    output reg clk_out
);
    always @(posedge clk_in) begin
        clk_out <= ~clk_out; // Divides by 2, not 3
    end
endmodule

/* Correct approach: count to 2 then toggle */
module correct_div_by_3(
    input wire clk_in,
    input wire reset,
    output reg clk_out
);
    reg [1:0] count = 0;
    always @(posedge clk_in or posedge reset) begin
        if (reset) begin
            count <= 0;
            clk_out <= 0;
        end else if (count == 2) begin
            count <= 0;
            clk_out <= ~clk_out;
        end else begin
            count <= count + 1;
        end
    end
endmodule

Quick Reference

Tips for frequency divider by 3 in Verilog:

• Use a 2-bit counter to count 0,1,2.
• Toggle output clock only when counter resets.
• Include asynchronous reset for reliable startup.
• Test with a simulation to verify timing.

Key Takeaways

Use a 2-bit counter to count input clock cycles up to 2 for dividing by 3.

Toggle the output clock only when the counter resets to zero.

Include a reset signal to initialize the counter and output clock.

Avoid toggling output on every clock edge as it divides frequency by 2, not 3.

Simulate your design to verify correct frequency division behavior.