How to Model NOT Gate in Verilog: Syntax and Example

In Verilog, you can model a NOT gate using the not keyword followed by the output and input signals in parentheses. For example, not (out, in); in a module defines the output as the logical NOT of the input.

Syntax

The basic syntax to model a NOT gate in Verilog uses the not gate primitive. It takes two arguments: the output signal and the input signal.

• not: keyword to define NOT gate
• (output, input): output and input signals in parentheses
• ;: ends the statement

verilog

not (out, in);

Example

This example shows a simple Verilog module that models a NOT gate. The output y is the logical NOT of input a. The testbench applies values to a and displays the output.

verilog

module not_gate(output y, input a);
  not (y, a);
endmodule

module test_not_gate;
  reg a;
  wire y;

  not_gate uut(y, a);

  initial begin
    $monitor("a = %b, y = %b", a, y);
    a = 0; #10;
    a = 1; #10;
    $finish;
  end
endmodule

Output

a = 0, y = 1
a = 1, y = 0

Common Pitfalls

Common mistakes when modeling a NOT gate in Verilog include:

• Forgetting to connect the output and input signals in the correct order.
• Using = assignment inside gate primitives instead of the gate syntax.
• Not declaring signals properly as wire or reg where needed.

Always use the gate primitive syntax not (out, in); inside a module.

verilog

/* Wrong way: Using assignment instead of gate primitive */
module wrong_not(output y, input a);
  assign y = ~a; // This works but is not gate primitive
endmodule

/* Right way: Using gate primitive */
module right_not(output y, input a);
  not (y, a);
endmodule

Quick Reference

Remember these tips when modeling NOT gates in Verilog:

• Use not (out, in); for gate-level modeling.
• Declare outputs as wire by default.
• Test your module with a simple testbench to verify behavior.

Key Takeaways

Use the gate primitive syntax not (out, in); to model a NOT gate in Verilog.

Ensure output and input signals are connected in the correct order inside the parentheses.

Declare signals properly and use a testbench to verify your NOT gate behavior.

Avoid using assignment operators when modeling gate primitives for clarity.

The NOT gate output is the logical inverse of the input signal.