What Is Synthesizable Verilog Code: Definition and Examples

Synthesizable Verilog code is Verilog code written in a way that can be converted by synthesis tools into real hardware circuits like gates and flip-flops. It uses only constructs that hardware can implement, avoiding simulation-only features.

How It Works

Think of synthesizable Verilog code as a recipe that a machine can follow to build a physical circuit. Just like a cooking recipe must use ingredients and steps that exist in the kitchen, synthesizable code must use only hardware-friendly instructions. This means it describes logic that can be made with real electronic parts like AND gates, registers, and multiplexers.

When you write synthesizable Verilog, you focus on describing what the hardware should do, not how to simulate or test it. The synthesis tool reads this code and creates a blueprint for the actual chip or FPGA. If the code uses unsupported features, the tool cannot make hardware from it, similar to how a recipe with imaginary ingredients can't be cooked.

Example

This example shows a simple synthesizable Verilog module that implements a 2-bit counter. It uses only hardware-friendly constructs like registers and always blocks triggered by a clock.

verilog

module counter(
    input wire clk,
    input wire reset,
    output reg [1:0] count
);

always @(posedge clk or posedge reset) begin
    if (reset) begin
        count <= 2'b00;
    end else begin
        count <= count + 1;
    end
end

endmodule

When to Use

Use synthesizable Verilog code when you want to create real digital hardware like ASICs or FPGAs. This code is the bridge between your design ideas and actual circuits that run in devices. For example, if you want to build a custom processor, a communication controller, or any digital logic, you write synthesizable Verilog.

On the other hand, if you are only testing or simulating behavior without building hardware, you might use non-synthesizable features. But for any real chip design, synthesizable code is essential.

Key Points

• Synthesizable Verilog describes hardware that can be physically built.
• It uses only constructs supported by synthesis tools.
• Non-synthesizable code is for simulation and testing only.
• Always blocks triggered by clocks and registers are common in synthesizable code.
• Understanding synthesizable code is key to digital hardware design.

Key Takeaways

Synthesizable Verilog code can be turned into real hardware circuits by synthesis tools.

It uses only hardware-implementable constructs like registers and combinational logic.

Non-synthesizable features are for simulation and cannot create hardware.

Writing synthesizable code is essential for FPGA and ASIC design.

Always test your code with synthesis tools to ensure it is synthesizable.