Verilog Code for Booth Multiplier: Syntax and Example

A Booth multiplier in Verilog uses Booth's algorithm to multiply signed numbers efficiently by encoding the multiplier bits. The code typically includes registers for multiplicand, multiplier, and product, and a control logic to perform shifts and additions based on Booth encoding.

Syntax

The Booth multiplier module usually has inputs for the multiplicand and multiplier, a clock and reset signal, and an output for the product. Inside, it uses registers to hold intermediate values and a state machine or control logic to perform the multiplication steps.

• Inputs: multiplicand, multiplier, clock, reset
• Outputs: product
• Registers: to store partial products and control bits
• Control logic: to decide when to add, subtract, or shift based on Booth encoding

verilog

module booth_multiplier(
    input wire clk,
    input wire reset,
    input wire signed [7:0] multiplicand,
    input wire signed [7:0] multiplier,
    output reg signed [15:0] product
);

    reg signed [15:0] A, Q, M;
    reg Q_1;
    reg [3:0] count;

    always @(posedge clk or posedge reset) begin
        if (reset) begin
            A <= 0;
            Q <= 0;
            M <= 0;
            Q_1 <= 0;
            count <= 0;
            product <= 0;
        end else if (count == 0) begin
            A <= 0;
            Q <= multiplier;
            M <= multiplicand;
            Q_1 <= 0;
            count <= 8;
        end else if (count > 0) begin
            case ({Q[0], Q_1})
                2'b01: A <= A + M; // Add multiplicand
                2'b10: A <= A - M; // Subtract multiplicand
                default: A <= A;  // No operation
            endcase
            // Arithmetic right shift of {A, Q, Q_1}
            {A, Q, Q_1} <= {A[15], A, Q} >>> 1;
            count <= count - 1;
            if (count == 1) product <= {A, Q};
        end
    end
endmodule

Example

This example shows a simple 8-bit Booth multiplier module that multiplies two signed 8-bit numbers and outputs a 16-bit product. It uses a clock and reset to control the operation and performs the multiplication over multiple clock cycles.

verilog

module testbench();
    reg clk;
    reg reset;
    reg signed [7:0] multiplicand;
    reg signed [7:0] multiplier;
    wire signed [15:0] product;

    booth_multiplier uut(
        .clk(clk),
        .reset(reset),
        .multiplicand(multiplicand),
        .multiplier(multiplier),
        .product(product)
    );

    initial begin
        clk = 0;
        forever #5 clk = ~clk; // 10 time units clock period
    end

    initial begin
        reset = 1;
        multiplicand = 8'd13;  // 13
        multiplier = -8'd3;    // -3
        #10;
        reset = 0;
        #160; // wait for multiplication to complete
        $display("Multiplicand: %d, Multiplier: %d, Product: %d", multiplicand, multiplier, product);
        $finish;
    end
endmodule

Output

Multiplicand: 13, Multiplier: -3, Product: -39

Common Pitfalls

Common mistakes when writing a Booth multiplier in Verilog include:

• Not handling signed numbers correctly, which leads to wrong results.
• Incorrectly implementing the arithmetic right shift, which must preserve the sign bit.
• Forgetting to initialize registers properly on reset.
• Not updating the product output at the right time after all cycles complete.

Always test with positive and negative values to verify correctness.

verilog

/* Wrong: Logical right shift loses sign bit */
// {A, Q, Q_1} <= {A, Q, Q_1} >> 1;

/* Correct: Arithmetic right shift preserves sign bit */
// {A, Q, Q_1} <= {A[15], A, Q} >>> 1;

Quick Reference

• Booth encoding: Look at two bits (current and previous) to decide add, subtract, or no operation.
• Registers: Use extended width registers to hold partial results.
• Shift: Use arithmetic right shift to maintain sign.
• Control: Count cycles equal to multiplier bit width.
• Reset: Initialize all registers to zero.

Key Takeaways

Booth multiplier uses bit pairs to reduce the number of additions and subtractions in signed multiplication.

Use arithmetic right shift (>>> in Verilog) to preserve the sign bit during shifting.

Initialize all registers properly on reset to avoid incorrect results.

Update the product output only after completing all multiplication cycles.

Test with both positive and negative inputs to ensure correctness.