Verilog Code for Multiplier: Syntax and Example

A multiplier in Verilog can be created using the * operator inside an assign statement or within an always block. The basic syntax involves declaring input operands and an output product, then assigning the product as the multiplication of inputs.

Syntax

The basic syntax for a multiplier in Verilog uses the * operator to multiply two inputs. You declare inputs and outputs, then assign the product.

• module: Defines the multiplier block.
• input: The numbers to multiply.
• output: The result of multiplication.
• assign: Continuously assigns the product of inputs to output.

verilog

module multiplier(
    input [3:0] a,
    input [3:0] b,
    output [7:0] product
);

assign product = a * b;

endmodule

Example

This example shows a 4-bit multiplier module that multiplies two 4-bit inputs and outputs an 8-bit product. It demonstrates simple combinational multiplication using the * operator.

verilog

module multiplier(
    input [3:0] a,
    input [3:0] b,
    output [7:0] product
);

assign product = a * b;

endmodule

// Testbench to simulate the multiplier
module testbench();
    reg [3:0] a, b;
    wire [7:0] product;

    multiplier uut(.a(a), .b(b), .product(product));

    initial begin
        a = 4'd3; b = 4'd4; // 3 * 4 = 12
        #10;
        $display("a=%d, b=%d, product=%d", a, b, product);

        a = 4'd7; b = 4'd8; // 7 * 8 = 56
        #10;
        $display("a=%d, b=%d, product=%d", a, b, product);

        a = 4'd15; b = 4'd15; // 15 * 15 = 225
        #10;
        $display("a=%d, b=%d, product=%d", a, b, product);

        $finish;
    end
endmodule

Output

a=3, b=4, product=12
a=7, b=8, product=56
a=15, b=15, product=225

Common Pitfalls

Common mistakes when writing a multiplier in Verilog include:

• Not declaring the output width wide enough to hold the product, causing overflow.
• Using blocking assignments (=) inside combinational logic incorrectly.
• Forgetting to use wire or reg types properly for outputs.
• Trying to multiply signed and unsigned numbers without proper casting.

Always ensure output width is the sum of input widths to avoid data loss.

verilog

/* Wrong: output width too small, causes overflow */
module wrong_multiplier(
    input [3:0] a,
    input [3:0] b,
    output [3:0] product // Too small for product
);

assign product = a * b;

endmodule

/* Right: output width is sum of input widths */
module correct_multiplier(
    input [3:0] a,
    input [3:0] b,
    output [7:0] product
);

assign product = a * b;

endmodule

Quick Reference

Tips for writing multipliers in Verilog:

• Use assign product = a * b; for simple combinational multiplication.
• Declare output width as sum of input widths (e.g., 4-bit inputs → 8-bit output).
• Use reg type if multiplication is inside always block.
• For signed multiplication, declare inputs and outputs as signed.

Key Takeaways

Use the * operator with assign to create a simple multiplier in Verilog.

Always declare output width as the sum of input widths to avoid overflow.

Use reg type for outputs if multiplication is inside an always block.

Be careful with signed vs unsigned inputs to get correct multiplication results.