Verilog Code for SR Flip Flop: Syntax and Example

An SR flip flop in Verilog can be coded using an always block sensitive to S and R inputs. The output Q sets to 1 when S=1, resets to 0 when R=1, and holds its value when both are 0. The invalid state when both S and R are 1 should be avoided or handled explicitly.

Syntax

The SR flip flop in Verilog uses an always block triggered by changes in S or R. Inside, if conditions check the inputs to set or reset the output Q. The else condition holds the previous state.

• S: Set input, sets Q to 1.
• R: Reset input, sets Q to 0.
• Q: Output storing the flip flop state.

verilog

module sr_flip_flop(input S, input R, output reg Q);
  always @(S or R) begin
    if (S == 1 && R == 0)
      Q = 1;
    else if (S == 0 && R == 1)
      Q = 0;
    else if (S == 0 && R == 0)
      Q = Q; // hold state
    else
      Q = 1'bx; // invalid state
  end
endmodule

Example

This example shows a testbench that applies different S and R inputs to the SR flip flop and prints the output Q. It demonstrates setting, resetting, holding, and the invalid state.

verilog

module sr_flip_flop(input S, input R, output reg Q);
  always @(S or R) begin
    if (S == 1 && R == 0)
      Q = 1;
    else if (S == 0 && R == 1)
      Q = 0;
    else if (S == 0 && R == 0)
      Q = Q; // hold state
    else
      Q = 1'bx; // invalid state
  end
endmodule

module testbench;
  reg S, R;
  wire Q;
  sr_flip_flop uut(S, R, Q);

  initial begin
    $monitor("At time %0t: S=%b R=%b -> Q=%b", $time, S, R, Q);
    S = 0; R = 0; #10;
    S = 1; R = 0; #10;
    S = 0; R = 0; #10;
    S = 0; R = 1; #10;
    S = 0; R = 0; #10;
    S = 1; R = 1; #10; // invalid
    $finish;
  end
endmodule

Output

At time 0: S=0 R=0 -> Q=x
At time 10: S=1 R=0 -> Q=1
At time 20: S=0 R=0 -> Q=1
At time 30: S=0 R=1 -> Q=0
At time 40: S=0 R=0 -> Q=0
At time 50: S=1 R=1 -> Q=x

Common Pitfalls

Common mistakes when coding SR flip flops include:

• Not handling the invalid state when both S and R are 1, which leads to unpredictable output.
• Using blocking assignments (=) inside sequential logic without care, which can cause simulation mismatches.
• Not using reg type for output Q, causing synthesis errors.

Always explicitly define behavior for all input combinations to avoid latches or unknown states.

verilog

/* Wrong: No invalid state handling */
module sr_flip_flop_wrong(input S, input R, output reg Q);
  always @(S or R) begin
    if (S == 1)
      Q = 1;
    else if (R == 1)
      Q = 0;
  end
endmodule

/* Right: Explicit invalid state */
module sr_flip_flop_right(input S, input R, output reg Q);
  always @(S or R) begin
    if (S == 1 && R == 0)
      Q = 1;
    else if (S == 0 && R == 1)
      Q = 0;
    else if (S == 0 && R == 0)
      Q = Q;
    else
      Q = 1'bx; // invalid
  end
endmodule

Quick Reference

Remember these key points for SR flip flop in Verilog:

• S=1, R=0: Set output Q=1.
• S=0, R=1: Reset output Q=0.
• S=0, R=0: Hold previous state.
• S=1, R=1: Invalid state, avoid or define explicitly.
• Use reg type for output Q.
• Use always @(S or R) for combinational SR flip flop.

Key Takeaways

Use an always block sensitive to S and R inputs to model SR flip flop behavior.

Explicitly handle the invalid state when both S and R are 1 to avoid unknown outputs.

Output Q must be declared as reg to store state in Verilog.

Hold the previous state when both S and R are 0 to maintain flip flop memory.

Test your SR flip flop with all input combinations to verify correct behavior.