Blocking vs Nonblocking Assignment in Verilog: Key Differences and Usage

In Verilog, blocking assignment uses the = operator and executes statements sequentially, blocking the next statement until completion. Nonblocking assignment uses the <= operator and schedules updates to happen later, allowing parallel execution within a time step.

Quick Comparison

This table summarizes the main differences between blocking and nonblocking assignments in Verilog.

Aspect	Blocking Assignment (=)	Nonblocking Assignment (<=)
Execution Order	Sequential, next statement waits	Scheduled, executes in parallel after current time step
Use Case	Combinational logic modeling	Sequential logic (flip-flops, registers)
Effect on RHS Evaluation	Right-hand side evaluated immediately	Right-hand side evaluated immediately, but update delayed
Simulation Behavior	Updates variable instantly	Updates variable at end of time step
Common Mistake	Can cause race conditions in sequential logic	Avoids race conditions in clocked processes

Key Differences

Blocking assignment uses the = operator and executes statements in the order they appear. Each assignment must finish before the next starts, like following a recipe step-by-step. This makes it suitable for modeling combinational logic where outputs depend immediately on inputs.

Nonblocking assignment uses the <= operator and schedules the assignment to happen later, after all right-hand sides are evaluated. This allows multiple assignments to appear simultaneous, which is essential for modeling sequential logic like flip-flops where all registers update together on a clock edge.

Using blocking assignments in sequential logic can cause unexpected race conditions because variables update immediately, affecting subsequent statements in the same time step. Nonblocking assignments avoid this by updating variables only after all evaluations, ensuring consistent and predictable behavior in synchronous designs.

Code Comparison

Here is an example showing how blocking assignment models a simple sequential process with immediate updates.

verilog

module blocking_example();
  reg a, b, c;
  initial begin
    a = 0;
    b = 0;
    c = 0;
    a = 1;       // update a immediately
    b = a;       // b gets new a value (1)
    c = b;       // c gets new b value (1)
    $display("a=%b b=%b c=%b", a, b, c);
  end
endmodule

Output

a=1 b=1 c=1

Nonblocking Equivalent

The same logic using nonblocking assignments delays updates until the end of the time step, so variables do not see intermediate changes immediately.

verilog

module nonblocking_example();
  reg a, b, c;
  initial begin
    a = 0;
    b = 0;
    c = 0;
    a <= 1;      // schedule a update
    b <= a;      // b gets old a value (0)
    c <= b;      // c gets old b value (0)
    #1;          // wait for updates to apply
    $display("a=%b b=%b c=%b", a, b, c);
  end
endmodule

Output

a=1 b=0 c=0

When to Use Which

Choose blocking assignment (=) when modeling combinational logic where outputs must update immediately based on inputs, such as in always @(*) blocks. It is simple and intuitive for step-by-step logic.

Choose nonblocking assignment (<=) when modeling sequential logic like flip-flops and registers inside clocked always @(posedge clk) blocks. It prevents race conditions by updating all registers simultaneously at the end of the time step.

Using the correct assignment type ensures your Verilog code simulates and synthesizes as intended, avoiding subtle bugs in hardware behavior.

Key Takeaways

Blocking assignment (=) executes statements sequentially and updates variables immediately.

Nonblocking assignment (<=) schedules updates to happen after all right-hand sides are evaluated, enabling parallel updates.

Use blocking assignments for combinational logic and nonblocking assignments for sequential logic.

Nonblocking assignments help avoid race conditions in clocked processes.

Choosing the right assignment type is crucial for correct hardware simulation and synthesis.