How to Write Function in Verilog: Syntax and Examples

In Verilog, you write a function using the function keyword followed by the return type and name. The function contains input arguments and a body that returns a value by assigning to the function name. Functions help reuse code and simplify designs.

Syntax

A Verilog function starts with the function keyword, followed by the return type and function name. Inside, you declare input arguments and write the logic. The function must return a value by assigning to the function name. It ends with endfunction.

• function [return_type] function_name; - declares the function and its return type.
• input [type] arg; - declares input arguments.
• function body - contains statements and assigns the return value to the function name.
• endfunction - marks the end of the function.

verilog

function [7:0] add_two_numbers;
  input [7:0] a;
  input [7:0] b;
  begin
    add_two_numbers = a + b;
  end
endfunction

Example

This example shows a function add_two_numbers that takes two 8-bit inputs and returns their sum. The function is called inside a module to add two numbers and assign the result to an output.

verilog

module test_function;
  reg [7:0] x, y;
  wire [7:0] sum;

  // Function definition
  function [7:0] add_two_numbers;
    input [7:0] a;
    input [7:0] b;
    begin
      add_two_numbers = a + b;
    end
  endfunction

  assign sum = add_two_numbers(x, y);

  initial begin
    x = 8'd10;
    y = 8'd20;
    #1 $display("Sum of %d and %d is %d", x, y, sum);
  end
endmodule

Output

Sum of 10 and 20 is 30

Common Pitfalls

Common mistakes when writing Verilog functions include:

• Not declaring input arguments inside the function.
• Forgetting to assign the function name to the return value instead of using return keyword (Verilog uses the function name as the return variable).
• Using blocking assignments (=) incorrectly inside functions.
• Trying to use timing controls like #delay inside functions (not allowed).

Functions must be purely combinational and cannot contain delays or event controls.

verilog

/* Wrong way: missing input declarations and using return keyword */
function [7:0] wrong_func;
  begin
    // return 8'd5; // Incorrect in Verilog
    wrong_func = 8'd5; // Correct way to assign return value
  end
endfunction

/* Right way: declare inputs and assign function name */
function [7:0] right_func;
  input [7:0] val;
  begin
    right_func = val + 8'd5;
  end
endfunction

Quick Reference

• Use function and endfunction to define a function.
• Declare inputs inside the function.
• Assign the return value by setting the function name.
• Functions cannot have timing controls or delays.
• Functions are used for combinational logic and return a single value.

Key Takeaways

Define functions with the function name as the return variable in Verilog.

Declare all input arguments inside the function before using them.

Functions must be combinational and cannot include delays or timing controls.

Use functions to simplify and reuse combinational logic in your designs.

Always end functions with endfunction to mark their boundary.