Why FSM with output logic in Verilog? - Purpose & Use Cases

The Big Idea

What if your traffic light could never get stuck showing the wrong color again?

The Scenario

Imagine trying to control a traffic light manually by flipping switches for each light color and timing every change yourself.

You have to remember which light should be on and when to change it, all without making mistakes.

The Problem

Manually managing each output for every state is slow and confusing.

It's easy to forget to update outputs when states change, causing wrong signals or unsafe conditions.

As the system grows, keeping track of outputs becomes a big headache.

The Solution

Using an FSM with output logic lets you clearly define outputs tied to each state.

This way, outputs automatically update when the FSM changes state, reducing errors and making the design easier to understand and maintain.

Before vs After

✗ Before

always @(state) begin
  if (state == S0) output = 1;
  else if (state == S1) output = 0;
end

✓ After

always @(state) begin
  case(state)
    S0: output = 1;
    S1: output = 0;
  endcase
end

What It Enables

This approach makes building reliable, clear, and scalable digital controllers possible.

Real Life Example

Traffic lights use FSMs with output logic to safely switch lights based on timers and sensors without manual intervention.

Key Takeaways

Manual output control is error-prone and hard to maintain.

FSM with output logic ties outputs directly to states for clarity.

This method improves reliability and scalability in digital designs.

Practice

1. Which part of an FSM with output logic determines the output signals based only on the current state?

easy

A. Input decoder

B. Next state logic

C. State register

D. Output logic in a Moore machine

Solution

1. Step 1: Understand FSM output types

   In FSMs, Moore outputs depend only on the current state, while Mealy outputs depend on state and input.

2. Step 2: Identify output logic role

   The output logic in a Moore machine produces outputs based solely on the current state stored in the state register.

3. Final Answer:

   Output logic in a Moore machine -> Option D

4. Quick Check:

   Moore output = state only [OK]

Hint: Moore outputs depend only on state, not inputs [OK]

Common Mistakes:

• Confusing next state logic with output logic
• Thinking outputs depend on inputs in Moore FSM
• Mixing state register role with output logic

2. Which of the following is the correct Verilog syntax to declare a state register named state with 2 bits?

easy

A. reg [1:0] state;

B. wire [2:0] state;

C. reg state[1:0];

D. state reg [1:0];

Solution

1. Step 1: Recall Verilog register declaration

   Registers are declared with reg keyword followed by bit width in brackets, e.g., reg [1:0] for 2 bits.

2. Step 2: Check each option

   reg [1:0] state; correctly declares a 2-bit register named state. wire [2:0] state; uses wire and wrong width. reg state[1:0]; uses incorrect syntax for bit width. state reg [1:0]; has wrong keyword order.

3. Final Answer:

   reg [1:0] state; -> Option A

4. Quick Check:

   reg [1:0] state; is correct syntax [OK]

Hint: Use reg [width-1:0] name; for registers [OK]

Common Mistakes:

• Using wire instead of reg for state registers
• Incorrect bit width syntax like reg name[1:0]
• Wrong keyword order like state reg

3. Given this Verilog snippet for a Moore FSM output logic:

always @(state) begin
  case(state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    2'b10: out = 1'b0;
    default: out = 1'b0;
  endcase
end

What is the output out when state is 2'b01?

medium

A. 1'b0

B. Undefined

C. 1'b1

D. 2'b01

Solution

1. Step 1: Check case for state 2'b01

   The case statement sets out = 1'b1 when state is 2'b01.

2. Step 2: Confirm output value

   Since the state matches 2'b01, output out is assigned 1'b1.

3. Final Answer:

   1'b1 -> Option C

4. Quick Check:

   State 01 -> out = 1 [OK]

Hint: Match state in case to find output quickly [OK]

Common Mistakes:

• Confusing output with state value
• Assuming default applies instead of matching case
• Misreading bit values as decimal

4. Identify the error in this FSM output logic code snippet:

always @(posedge clk) begin
  case(state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    default: out = 1'b0;
  endcase
end

What is the main problem?

medium

A. Output logic should be in a combinational always block, not clocked

B. Missing reset signal for output

C. State values are incorrectly formatted

D. Output out is not declared as reg

Solution

1. Step 1: Understand output logic timing

   Moore FSM output logic is usually combinational and depends only on state, so it should be in an always block sensitive to state changes, not clock edges.

2. Step 2: Analyze given code

   The code uses always @(posedge clk), making output synchronous, which is incorrect for pure output logic in Moore FSM.

3. Final Answer:

   Output logic should be in a combinational always block, not clocked -> Option A

4. Quick Check:

   Output logic = combinational, not clocked [OK]

Hint: Output logic usually uses always @(*) for combinational [OK]

Common Mistakes:

• Using clocked always block for output logic
• Ignoring sensitivity list correctness
• Confusing output and state update blocks

5. You want to design a Mealy FSM with output logic that sets out = 1 only when the current state is 2'b10 and input in is high. Which Verilog code snippet correctly implements this output logic?

hard

A. always @(in) begin\n if (in)\n out = 1'b1;\n else\n out = 1'b0;\nend

B. always @(state or in) begin\n if (state == 2'b10 && in)\n out = 1'b1;\n else\n out = 1'b0;\nend

C. always @(posedge clk) begin\n if (state == 2'b10 && in)\n out <= 1'b1;\n else\n out <= 1'b0;\nend

D. always @(state) begin\n if (state == 2'b10)\n out = 1'b1;\n else\n out = 1'b0;\nend

Solution

1. Step 1: Understand Mealy output logic

   Mealy outputs depend on both current state and inputs, so sensitivity list must include both state and in.

2. Step 2: Check each option

   always @(state or in) begin\n if (state == 2'b10 && in)\n out = 1'b1;\n else\n out = 1'b0;\nend correctly uses always @(state or in) and sets out based on both conditions. always @(state) begin\n if (state == 2'b10)\n out = 1'b1;\n else\n out = 1'b0;\nend ignores input in. always @(posedge clk) begin\n if (state == 2'b10 && in)\n out <= 1'b1;\n else\n out <= 1'b0;\nend uses clocked block which is not typical for Mealy output logic. always @(in) begin\n if (in)\n out = 1'b1;\n else\n out = 1'b0;\nend ignores state.

3. Final Answer:

   always @(state or in) begin if (state == 2'b10 && in) out = 1'b1; else out = 1'b0; end -> Option B

4. Quick Check:

   Mealy output depends on state and input [OK]

Hint: Include both state and input in sensitivity list for Mealy outputs [OK]

Common Mistakes:

• Leaving input out of sensitivity list
• Using clocked always block for Mealy output
• Ignoring state condition in output logic