Why FSM with output logic in Verilog? - Purpose & Use Cases

The Big Idea

What if your traffic light could never get stuck showing the wrong color again?

The Scenario

Imagine trying to control a traffic light manually by flipping switches for each light color and timing every change yourself.

You have to remember which light should be on and when to change it, all without making mistakes.

The Problem

Manually managing each output for every state is slow and confusing.

It's easy to forget to update outputs when states change, causing wrong signals or unsafe conditions.

As the system grows, keeping track of outputs becomes a big headache.

The Solution

Using an FSM with output logic lets you clearly define outputs tied to each state.

This way, outputs automatically update when the FSM changes state, reducing errors and making the design easier to understand and maintain.

Before vs After

✗ Before

always @(state) begin
  if (state == S0) output = 1;
  else if (state == S1) output = 0;
end

✓ After

always @(state) begin
  case(state)
    S0: output = 1;
    S1: output = 0;
  endcase
end

What It Enables

This approach makes building reliable, clear, and scalable digital controllers possible.

Real Life Example

Traffic lights use FSMs with output logic to safely switch lights based on timers and sensors without manual intervention.

Key Takeaways

Manual output control is error-prone and hard to maintain.

FSM with output logic ties outputs directly to states for clarity.

This method improves reliability and scalability in digital designs.