Why always blocks are needed in Verilog

Introduction

Always blocks let you describe how parts of a digital circuit change over time. They help you write rules that say what happens when inputs change or when a clock ticks.

To describe how a flip-flop updates its output on a clock edge.

To model combinational logic that reacts immediately when inputs change.

To create sequential logic that depends on past values and timing.

To group multiple statements that should run together when signals change.

Syntax

Verilog

always @(sensitivity_list) begin
  // statements
end

The sensitivity_list tells when the block should run, like on a clock edge or when inputs change.

You can use 'always @*' to automatically include all inputs for combinational logic.

Examples

This runs on the rising edge of the clock to update a flip-flop output.

Verilog

always @(posedge clk) begin
  q <= d;
end

This runs whenever inputs 'a' or 'b' change to update output 'y' immediately.

Verilog

always @(*) begin
  y = a & b;
end

Sample Program

This module uses an always block to update 'q' with 'd' on each rising clock edge, modeling a simple flip-flop.

Verilog

module simple_ff(
  input wire clk,
  input wire d,
  output reg q
);

always @(posedge clk) begin
  q <= d;
end

endmodule

Important Notes

Always blocks are essential because they let you describe both combinational and sequential logic clearly.

Without always blocks, you cannot model how signals change over time in hardware.

Summary

Always blocks run code when signals change or on clock edges.

They help describe how hardware behaves over time.

Use them to write both combinational and sequential logic.