FSM with output logic in Verilog - Step-by-Step Execution

Concept Flow - FSM with output logic

Start: Reset State

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Check Input

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Transition to Next State

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Update Output Based on State

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Wait for Next Clock

↩Back to Check Input

The FSM starts at a reset state, checks inputs, moves to the next state, updates outputs based on the current state, then waits for the next clock cycle to repeat.

Execution Sample

Verilog

module fsm_output(
  input clk, reset, in,
  output reg out
);
  typedef enum logic [1:0] {S0, S1} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end

  always_comb begin
    next_state = state;
    out = 0;
    case(state)
      S0: if (in) next_state = S1;
      S1: begin
        out = 1;
        if (!in) next_state = S0;
      end
    endcase
  end
endmodule

This Verilog FSM has two states S0 and S1, changes state based on input 'in', and sets output 'out' depending on the current state.

Execution Table

Step	clk	reset	in	state (before)	next_state	state (after)	out
1	0	1	0	X	S0	S0	0
2	1	0	0	S0	S0	S0	0
3	0	0	1	S0	S1	S0	0
4	1	0	1	S0	S1	S1	1
5	0	0	1	S1	S1	S1	1
6	1	0	0	S1	S0	S0	1
7	0	0	0	S0	S0	S0	0
8	1	0	0	S0	S0	S0	0
9	0	0	0	S0	S0	S0	0

💡 Simulation ends after several clock cycles showing state transitions and output changes.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	Final
state	X	S0	S0	S0	S1	S1	S0	S0	S0
next_state	S0	S0	S1	S1	S1	S0	S0	S0	S0
out	0	0	0	0	1	1	0	0	0
in	0	0	1	1	1	0	0	0	0
reset	1	0	0	0	0	0	0	0	0
clk	0	1	0	1	0	1	0	1	0

Key Moments - 3 Insights

Why does the output 'out' become 1 only in state S1?

Because in the always_comb block, 'out' is set to 1 only when the FSM is in state S1 (see execution_table rows 4-6). In S0, 'out' remains 0.

Why does the state update happen only on the clock's rising edge?

The always_ff block triggers on posedge clk, so state changes only at clock rising edges (see execution_table steps where clk=1 and state changes).

What happens when reset is high?

When reset is 1, the state immediately goes to S0 regardless of input (see step 1 in execution_table). This initializes the FSM.

Visual Quiz - 3 Questions

Look at the execution_table at step 4. What is the state after the clock edge?

A S0

B S1

C X (undefined)

D S2 (nonexistent)

💡 Hint

Check the 'state (after)' column at step 4 in the execution_table.

At which step does the output 'out' first become 1?

A Step 3

B Step 2

C Step 5

D Step 1

💡 Hint

Look at the 'out' column in execution_table and find when it changes from 0 to 1.

If the input 'in' stayed 0 after step 8, what would be the next state?

A S0

B S2

C S1

D Undefined

💡 Hint

Refer to the transition logic in the code and the last state in variable_tracker.

Concept Snapshot

FSM with output logic in Verilog:
- Use always_ff for state updates on clock edge
- Use always_comb for next_state and output logic
- Output depends on current state
- Reset initializes state
- State transitions depend on inputs

Full Transcript

This visual trace shows a simple FSM in Verilog with two states S0 and S1. The FSM starts at S0 after reset. On each clock rising edge, it updates its state based on input 'in'. The output 'out' is 1 only in state S1. The execution table tracks clock, reset, input, current state, next state, and output step-by-step. The variable tracker shows how each variable changes over time. Key moments clarify why output depends on state, why state updates on clock edges, and the effect of reset. The quiz tests understanding of state changes and output timing.