FSM with output logic in Verilog - Step-by-Step Execution

Concept Flow - FSM with output logic

Start: Reset State

↓

Check Input

↓

Transition to Next State

↓

Update Output Based on State

↓

Wait for Next Clock

↩Back to Check Input

The FSM starts at a reset state, checks inputs, moves to the next state, updates outputs based on the current state, then waits for the next clock cycle to repeat.

Execution Sample

Verilog

module fsm_output(
  input clk, reset, in,
  output reg out
);
  typedef enum logic [1:0] {S0, S1} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end

  always_comb begin
    next_state = state;
    out = 0;
    case(state)
      S0: if (in) next_state = S1;
      S1: begin
        out = 1;
        if (!in) next_state = S0;
      end
    endcase
  end
endmodule

This Verilog FSM has two states S0 and S1, changes state based on input 'in', and sets output 'out' depending on the current state.

Execution Table

Step	clk	reset	in	state (before)	next_state	state (after)	out
1	0	1	0	X	S0	S0	0
2	1	0	0	S0	S0	S0	0
3	0	0	1	S0	S1	S0	0
4	1	0	1	S0	S1	S1	1
5	0	0	1	S1	S1	S1	1
6	1	0	0	S1	S0	S0	1
7	0	0	0	S0	S0	S0	0
8	1	0	0	S0	S0	S0	0
9	0	0	0	S0	S0	S0	0

💡 Simulation ends after several clock cycles showing state transitions and output changes.

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	After 6	After 7	Final
state	X	S0	S0	S0	S1	S1	S0	S0	S0
next_state	S0	S0	S1	S1	S1	S0	S0	S0	S0
out	0	0	0	0	1	1	0	0	0
in	0	0	1	1	1	0	0	0	0
reset	1	0	0	0	0	0	0	0	0
clk	0	1	0	1	0	1	0	1	0

Key Moments - 3 Insights

Why does the output 'out' become 1 only in state S1?

Because in the always_comb block, 'out' is set to 1 only when the FSM is in state S1 (see execution_table rows 4-6). In S0, 'out' remains 0.

Why does the state update happen only on the clock's rising edge?

The always_ff block triggers on posedge clk, so state changes only at clock rising edges (see execution_table steps where clk=1 and state changes).

What happens when reset is high?

When reset is 1, the state immediately goes to S0 regardless of input (see step 1 in execution_table). This initializes the FSM.

Visual Quiz - 3 Questions

Look at the execution_table at step 4. What is the state after the clock edge?

A S0

B S1

C X (undefined)

D S2 (nonexistent)

💡 Hint

Check the 'state (after)' column at step 4 in the execution_table.

At which step does the output 'out' first become 1?

A Step 3

B Step 2

C Step 5

D Step 1

💡 Hint

Look at the 'out' column in execution_table and find when it changes from 0 to 1.

If the input 'in' stayed 0 after step 8, what would be the next state?

A S0

B S2

C S1

D Undefined

💡 Hint

Refer to the transition logic in the code and the last state in variable_tracker.

Concept Snapshot

FSM with output logic in Verilog:
- Use always_ff for state updates on clock edge
- Use always_comb for next_state and output logic
- Output depends on current state
- Reset initializes state
- State transitions depend on inputs

Full Transcript

This visual trace shows a simple FSM in Verilog with two states S0 and S1. The FSM starts at S0 after reset. On each clock rising edge, it updates its state based on input 'in'. The output 'out' is 1 only in state S1. The execution table tracks clock, reset, input, current state, next state, and output step-by-step. The variable tracker shows how each variable changes over time. Key moments clarify why output depends on state, why state updates on clock edges, and the effect of reset. The quiz tests understanding of state changes and output timing.

Practice

1. Which part of an FSM with output logic determines the output signals based only on the current state?

easy

A. Input decoder

B. Next state logic

C. State register

D. Output logic in a Moore machine

Solution

1. Step 1: Understand FSM output types

   In FSMs, Moore outputs depend only on the current state, while Mealy outputs depend on state and input.

2. Step 2: Identify output logic role

   The output logic in a Moore machine produces outputs based solely on the current state stored in the state register.

3. Final Answer:

   Output logic in a Moore machine -> Option D

4. Quick Check:

   Moore output = state only [OK]

Hint: Moore outputs depend only on state, not inputs [OK]

Common Mistakes:

• Confusing next state logic with output logic
• Thinking outputs depend on inputs in Moore FSM
• Mixing state register role with output logic

2. Which of the following is the correct Verilog syntax to declare a state register named state with 2 bits?

easy

A. reg [1:0] state;

B. wire [2:0] state;

C. reg state[1:0];

D. state reg [1:0];

Solution

1. Step 1: Recall Verilog register declaration

   Registers are declared with reg keyword followed by bit width in brackets, e.g., reg [1:0] for 2 bits.

2. Step 2: Check each option

   reg [1:0] state; correctly declares a 2-bit register named state. wire [2:0] state; uses wire and wrong width. reg state[1:0]; uses incorrect syntax for bit width. state reg [1:0]; has wrong keyword order.

3. Final Answer:

   reg [1:0] state; -> Option A

4. Quick Check:

   reg [1:0] state; is correct syntax [OK]

Hint: Use reg [width-1:0] name; for registers [OK]

Common Mistakes:

• Using wire instead of reg for state registers
• Incorrect bit width syntax like reg name[1:0]
• Wrong keyword order like state reg

3. Given this Verilog snippet for a Moore FSM output logic:

always @(state) begin
  case(state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    2'b10: out = 1'b0;
    default: out = 1'b0;
  endcase
end

What is the output out when state is 2'b01?

medium

A. 1'b0

B. Undefined

C. 1'b1

D. 2'b01

Solution

1. Step 1: Check case for state 2'b01

   The case statement sets out = 1'b1 when state is 2'b01.

2. Step 2: Confirm output value

   Since the state matches 2'b01, output out is assigned 1'b1.

3. Final Answer:

   1'b1 -> Option C

4. Quick Check:

   State 01 -> out = 1 [OK]

Hint: Match state in case to find output quickly [OK]

Common Mistakes:

• Confusing output with state value
• Assuming default applies instead of matching case
• Misreading bit values as decimal

4. Identify the error in this FSM output logic code snippet:

always @(posedge clk) begin
  case(state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    default: out = 1'b0;
  endcase
end

What is the main problem?

medium

A. Output logic should be in a combinational always block, not clocked

B. Missing reset signal for output

C. State values are incorrectly formatted

D. Output out is not declared as reg

Solution

1. Step 1: Understand output logic timing

   Moore FSM output logic is usually combinational and depends only on state, so it should be in an always block sensitive to state changes, not clock edges.

2. Step 2: Analyze given code

   The code uses always @(posedge clk), making output synchronous, which is incorrect for pure output logic in Moore FSM.

3. Final Answer:

   Output logic should be in a combinational always block, not clocked -> Option A

4. Quick Check:

   Output logic = combinational, not clocked [OK]

Hint: Output logic usually uses always @(*) for combinational [OK]

Common Mistakes:

• Using clocked always block for output logic
• Ignoring sensitivity list correctness
• Confusing output and state update blocks

5. You want to design a Mealy FSM with output logic that sets out = 1 only when the current state is 2'b10 and input in is high. Which Verilog code snippet correctly implements this output logic?

hard

A. always @(in) begin\n if (in)\n out = 1'b1;\n else\n out = 1'b0;\nend

B. always @(state or in) begin\n if (state == 2'b10 && in)\n out = 1'b1;\n else\n out = 1'b0;\nend

C. always @(posedge clk) begin\n if (state == 2'b10 && in)\n out <= 1'b1;\n else\n out <= 1'b0;\nend

D. always @(state) begin\n if (state == 2'b10)\n out = 1'b1;\n else\n out = 1'b0;\nend

Solution

1. Step 1: Understand Mealy output logic

   Mealy outputs depend on both current state and inputs, so sensitivity list must include both state and in.

2. Step 2: Check each option

   always @(state or in) begin\n if (state == 2'b10 && in)\n out = 1'b1;\n else\n out = 1'b0;\nend correctly uses always @(state or in) and sets out based on both conditions. always @(state) begin\n if (state == 2'b10)\n out = 1'b1;\n else\n out = 1'b0;\nend ignores input in. always @(posedge clk) begin\n if (state == 2'b10 && in)\n out <= 1'b1;\n else\n out <= 1'b0;\nend uses clocked block which is not typical for Mealy output logic. always @(in) begin\n if (in)\n out = 1'b1;\n else\n out = 1'b0;\nend ignores state.

3. Final Answer:

   always @(state or in) begin if (state == 2'b10 && in) out = 1'b1; else out = 1'b0; end -> Option B

4. Quick Check:

   Mealy output depends on state and input [OK]

Hint: Include both state and input in sensitivity list for Mealy outputs [OK]

Common Mistakes:

• Leaving input out of sensitivity list
• Using clocked always block for Mealy output
• Ignoring state condition in output logic