Shift register (SIPO, PISO, SISO) in Verilog

Introduction

A shift register moves data bits in a sequence, one step at a time. It helps change data from serial to parallel or parallel to serial form.

When you want to convert serial data into parallel data (SIPO).

When you want to convert parallel data into serial data (PISO).

When you want to move data bit by bit in the same format (SISO).

When building simple memory or delay circuits.

When you need to control data flow in communication systems.

Syntax

Verilog

module shift_register(
    input clk,
    input reset,
    input serial_in,
    input [N-1:0] parallel_in,
    input load,
    output reg serial_out,
    output reg [N-1:0] parallel_out
);

    // Shift register logic here

endmodule

clk is the clock signal that controls timing.

reset clears the register to zero.

Examples

This is a Serial-In Serial-Out (SISO) shift register with 4 bits.

Verilog

module SISO_shift_register(
    input clk,
    input reset,
    input serial_in,
    output reg serial_out
);
    reg [3:0] shift_reg;
    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_reg <= 4'b0000;
        else begin
            serial_out <= shift_reg[3];
            shift_reg <= {shift_reg[2:0], serial_in};
        end
    end
endmodule

This is a Serial-In Parallel-Out (SIPO) shift register with 4 bits.

Verilog

module SIPO_shift_register(
    input clk,
    input reset,
    input serial_in,
    output reg [3:0] parallel_out
);
    reg [3:0] shift_reg;
    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_reg <= 4'b0000;
        else
            shift_reg <= {shift_reg[2:0], serial_in};
    end
    always @(*) begin
        parallel_out = shift_reg;
    end
endmodule

This is a Parallel-In Serial-Out (PISO) shift register with 4 bits.

Verilog

module PISO_shift_register(
    input clk,
    input reset,
    input load,
    input [3:0] parallel_in,
    output reg serial_out
);
    reg [3:0] shift_reg;
    always @(posedge clk or posedge reset) begin
        if (reset)
            shift_reg <= 4'b0000;
        else if (load)
            shift_reg <= parallel_in;
        else
            shift_reg <= {shift_reg[2:0], 1'b0};
    end
    always @(*) begin
        serial_out = shift_reg[3];
    end
endmodule

Sample Program

This testbench runs all three types of shift registers. It shows how bits move through SISO and SIPO with serial input, and how PISO outputs serial data after loading parallel input.

Verilog

module test_shift_register();
    reg clk = 0;
    reg reset;
    reg serial_in;
    reg load;
    reg [3:0] parallel_in;
    wire serial_out_siso;
    wire [3:0] parallel_out_sipo;
    wire serial_out_piso;

    // Instantiate SISO
    SISO_shift_register siso(.clk(clk), .reset(reset), .serial_in(serial_in), .serial_out(serial_out_siso));

    // Instantiate SIPO
    SIPO_shift_register sipo(.clk(clk), .reset(reset), .serial_in(serial_in), .parallel_out(parallel_out_sipo));

    // Instantiate PISO
    PISO_shift_register piso(.clk(clk), .reset(reset), .load(load), .parallel_in(parallel_in), .serial_out(serial_out_piso));

    // Clock generation
    always #5 clk = ~clk;

    initial begin
        reset = 1; serial_in = 0; load = 0; parallel_in = 4'b1010;
        #10 reset = 0;

        // Test SISO and SIPO with serial input 1,0,1,1
        serial_in = 1; #10;
        serial_in = 0; #10;
        serial_in = 1; #10;
        serial_in = 1; #10;

        // Test PISO load and shift
        load = 1; #10;
        load = 0; #40;

        $finish;
    end

    initial begin
        $monitor($time, " clk=%b reset=%b serial_in=%b load=%b parallel_in=%b | SISO_out=%b SIPO_out=%b PISO_out=%b",
                 clk, reset, serial_in, load, parallel_in, serial_out_siso, parallel_out_sipo, serial_out_piso);
    end
endmodule

Important Notes

Shift registers work on clock edges, usually the rising edge.

Resetting clears all bits to zero.

Load signal in PISO controls when parallel data is loaded.

Summary

Shift registers move bits step-by-step controlled by a clock.

SISO shifts data serially in and out.

SIPO converts serial input to parallel output.

PISO converts parallel input to serial output.