A ring counter is a simple circuit that cycles a single '1' through a group of bits. It helps keep track of steps or states in a repeating pattern.
0
0
Ring counter in Verilog
Introduction
To create a simple sequence generator that repeats a pattern.
To control steps in a machine that moves in a circle or loop.
To divide a clock signal into equal parts for timing.
To cycle through LEDs one at a time in a repeating pattern.
Syntax
Verilog
module ring_counter(
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk or posedge reset) begin
if (reset)
q <= 4'b0001;
else
q <= {q[0], q[3:1]};
end
endmoduleThe module has a clock and reset input, and a 4-bit output.
On reset, the output sets to 0001, starting the ring.
Examples
This line shifts the bits to the right and wraps the rightmost bit to the left end, moving the '1' around.
Verilog
q <= {q[0], q[3:1]};When reset is pressed, the counter starts fresh with only the first bit set.
Verilog
if (reset) q <= 4'b0001;
Sample Program
This program defines a 4-bit ring counter and a testbench that toggles the clock and releases reset. It prints the output bits over time to show the '1' moving around.
Verilog
module ring_counter(
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk or posedge reset) begin
if (reset)
q <= 4'b0001;
else
q <= {q[0], q[3:1]};
end
endmodule
// Testbench to see the ring counter in action
module testbench();
reg clk = 0;
reg reset = 1;
wire [3:0] q;
ring_counter rc(.clk(clk), .reset(reset), .q(q));
always #5 clk = ~clk; // Clock toggles every 5 time units
initial begin
$monitor($time, " q = %b", q);
#10 reset = 0; // Release reset after 10 time units
#50 $finish; // Stop simulation after 50 time units
end
endmoduleOutputSuccess
Important Notes
The ring counter cycles through states with only one bit set at a time.
Make sure to reset the counter to start the ring properly.
The size of the ring counter depends on how many bits you use.
Summary
A ring counter moves a single '1' bit around a group of bits in a loop.
It is useful for simple step sequencing and timing tasks.
Resetting the counter sets the starting point for the cycle.