If-else in always blocks in Verilog

Introduction

If-else statements inside always blocks help decide what the circuit should do based on conditions.

To choose between two or more actions depending on input signals.

To create simple decision-making logic like turning on a light if a switch is pressed.

To update outputs differently based on different input values.

To model behavior that changes over time or with events.

To handle reset conditions separately from normal operation.

Syntax

Verilog

always @(sensitivity_list) begin
    if (condition) begin
        // statements when condition is true
    end else begin
        // statements when condition is false
    end
end

The always block runs whenever signals in the sensitivity list change.

Use begin and end to group multiple statements inside if or else.

Examples

On clock's rising edge, if reset is true, set q to 0; otherwise, set q to d.

Verilog

always @(posedge clk) begin
    if (reset) begin
        q <= 0;
    end else begin
        q <= d;
    end
end

Whenever a or b changes, output the bigger value.

Verilog

always @(a or b) begin
    if (a > b) out = a;
    else out = b;
end

Sample Program

This module sets output q to 0 when reset is high at clock's rising edge. Otherwise, it copies input d to q.

Verilog

module simple_if_else(
    input wire clk,
    input wire reset,
    input wire d,
    output reg q
);

always @(posedge clk) begin
    if (reset) begin
        q <= 0;
    end else begin
        q <= d;
    end
end

endmodule

Important Notes

Use non-blocking assignments (<=) inside clocked always blocks for correct timing.

Always include all conditions to avoid unintended latches.

The sensitivity list controls when the always block runs; for clocked logic, use posedge or negedge.

Summary

If-else inside always blocks lets you choose actions based on conditions.

Use begin and end to group multiple statements.

Always blocks run when signals in their sensitivity list change.

Practice

1. What is the main purpose of using if-else statements inside always blocks in Verilog?

easy

A. To declare variables

B. To create loops

C. To control hardware behavior based on conditions

D. To define module ports

Solution

1. Step 1: Understand the role of always blocks

   always blocks describe hardware that reacts to changes in signals.

2. Step 2: Understand if-else inside always

   if-else lets hardware choose different actions based on conditions.

3. Final Answer:

   To control hardware behavior based on conditions -> Option C

4. Quick Check:

   if-else controls hardware actions = B [OK]

Hint: If-else decides hardware action by condition [OK]

Common Mistakes:

• Thinking if-else declares variables
• Confusing if-else with loops
• Using if-else to define ports

2. Which of the following is the correct syntax for an if-else statement inside an always block in Verilog?

easy

A. always @ (posedge clk) if (a) begin b = 1; end else b = 0

B. always @ (posedge clk) if (a) b = 1; else b = 0;

C. always @ (posedge clk) if a { b = 1; } else { b = 0; }

D. always (posedge clk) if a then b = 1 else b = 0;

Solution

1. Step 1: Check the correct sensitivity list syntax

   It must be always @ (posedge clk), not missing @ or parentheses.

2. Step 2: Check if-else syntax

   Condition must be in parentheses, and statements can be single-line without begin-end.

3. Final Answer:

   always @ (posedge clk) if (a) b = 1; else b = 0; -> Option B

4. Quick Check:

   Correct always and if-else syntax = D [OK]

Hint: Use @ and parentheses for always and if conditions [OK]

Common Mistakes:

• Omitting @ in always sensitivity
• Missing parentheses around condition
• Using braces {} instead of begin-end

3. What will be the value of out after the following code runs if sel = 1 and in = 5?

always @(*) begin
  if (sel == 1)
    out = in + 1;
  else
    out = in - 1;
end

medium

A. 4

B. 5

C. Undefined

D. 6

Solution

1. Step 1: Check the condition with given inputs

   Since sel == 1 is true, the first branch executes.

2. Step 2: Calculate the assigned value

   out = in + 1 = 5 + 1 = 6.

3. Final Answer:

   6 -> Option D

4. Quick Check:

   sel=1 triggers out=in+1=6 [OK]

Hint: Follow if condition and calculate assigned value [OK]

Common Mistakes:

• Ignoring the if condition value
• Subtracting instead of adding
• Assuming out is unchanged

4. Identify the error in this Verilog code snippet:

always @ (posedge clk) begin
  if (reset == 1)
    count = 0;
  else if (enable == 1)
    count = count + 1;
end

medium

A. Using blocking assignment = instead of non-blocking <=

B. No default else to cover all cases

C. Missing begin-end after else if

D. Incorrect sensitivity list

Solution

1. Step 1: Check assignment type inside clocked always

   Inside clocked blocks, non-blocking assignments (<=) should be used for registers.

2. Step 2: Verify other parts

   Sensitivity list and if-else structure are correct; missing else is allowed but not best practice.

3. Final Answer:

   Using blocking assignment = instead of non-blocking <= -> Option A

4. Quick Check:

   Clocked always needs non-blocking <= [OK]

Hint: Use <= for assignments in clocked always blocks [OK]

Common Mistakes:

• Using = instead of <= in sequential logic
• Forgetting begin-end for multiple statements
• Ignoring missing else cases

5. You want to design a 2-bit saturating counter using an always block with if-else. The counter increments on enable and resets to 0 on reset. It saturates at 3 (does not wrap). Which code snippet correctly implements this behavior?

hard

A. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable && count < 3) count <= count + 1;
else count <= count;
end

B. always @ (posedge clk) begin
if (reset) count = 0;
else if (enable) count = (count == 3) ? 3 : count + 1;
end

C. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= count + 1;
if (count > 3) count <= 3;
end

D. always @ (posedge clk) begin
if (reset) count <= 0;
else if (enable) count <= (count == 3) ? 0 : count + 1;
end

Solution

1. Step 1: Check reset and enable behavior

   Reset sets count to 0; enable increments count only if less than 3.

2. Step 2: Verify saturation logic

   always @ (posedge clk) begin if (reset) count <= 0; else if (enable && count < 3) count <= count + 1; else count <= count; end increments only if count < 3, else holds count, correctly saturating at 3.

3. Step 3: Check assignment type and completeness

   Uses non-blocking <= and covers all cases with else count <= count.

4. Final Answer:

   always @ (posedge clk) begin if (reset) count <= 0; else if (enable && count < 3) count <= count + 1; else count <= count; end -> Option A

5. Quick Check:

   Saturate at 3 by conditional increment and hold = A [OK]

Hint: Increment only if less than max, else hold value [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Resetting incorrectly or missing saturation check
• Wrapping counter instead of saturating