Default case importance in Verilog

Introduction

The default case in a Verilog case statement ensures the circuit behaves predictably when none of the specified cases match. It helps avoid unexpected results and makes your design safer.

When you want to handle unexpected input values in a <code>case</code> statement.

When designing a finite state machine to cover all possible states.

When you want to assign a safe or known value if no case matches.

When you want to avoid latches by ensuring all outputs are assigned.

When you want to improve simulation and synthesis reliability.

Syntax

Verilog

case (expression)
  value1: begin
    // statements
  end
  value2: begin
    // statements
  end
  default: begin
    // statements for unmatched cases
  end
endcase

The default block runs if no other case matches.

Including default helps prevent unintended latches by ensuring all outputs get assigned.

Examples

If opcode is not 0001 or 0010, out is set to 0.

Verilog

case (opcode)
  4'b0001: out = 1;
  4'b0010: out = 2;
  default: out = 0;
endcase

Ensures next_state is always assigned, even if state is unexpected.

Verilog

case (state)
  IDLE: next_state = RUN;
  RUN: next_state = STOP;
  default: next_state = IDLE;
endcase

Sample Program

This example shows a case with a default that sets out to 0 if sel is not one of the listed cases. The testbench tests three values, including one that triggers the default.

Verilog

module default_case_example(input [1:0] sel, output reg [3:0] out);
  always @(*) begin
    case (sel)
      2'b00: out = 4'd1;
      2'b01: out = 4'd2;
      2'b10: out = 4'd3;
      default: out = 4'd0;
    endcase
  end
endmodule

// Testbench
module test;
  reg [1:0] sel;
  wire [3:0] out;
  default_case_example uut(sel, out);

  initial begin
    sel = 2'b00; #10;
    $display("sel=%b out=%d", sel, out);
    sel = 2'b01; #10;
    $display("sel=%b out=%d", sel, out);
    sel = 2'b11; #10;
    $display("sel=%b out=%d", sel, out);
    $finish;
  end
endmodule

Important Notes

Always include a default to avoid unintended latches in combinational logic.

Without default, synthesis tools might infer memory elements, which can cause bugs.

Default case improves code readability and safety.

Summary

The default case handles unexpected inputs safely.

It prevents unintended latches by ensuring all outputs are assigned.

Always use default in case statements for reliable designs.