Traffic light controller FSM in Verilog

Introduction

A traffic light controller FSM helps manage traffic lights automatically. It changes lights in a safe order to control cars and pedestrians.

To control traffic lights at a road intersection.

To manage pedestrian crossing signals safely.

To automate light changes based on time intervals.

To learn how simple machines control real-world devices.

Syntax

Verilog

module traffic_light_fsm(
    input clk,
    input reset,
    output reg [2:0] light
);

    typedef enum reg [1:0] {
        RED = 2'b00,
        GREEN = 2'b01,
        YELLOW = 2'b10
    } state_t;

    state_t state, next_state;

    // State transition logic
    always @(posedge clk or posedge reset) begin
        if (reset) state <= RED;
        else state <= next_state;
    end

    // Next state logic
    always @(*) begin
        case(state)
            RED: next_state = GREEN;
            GREEN: next_state = YELLOW;
            YELLOW: next_state = RED;
            default: next_state = RED;
        endcase
    end

    // Output logic
    always @(*) begin
        case(state)
            RED: light = 3'b100;    // Red light on
            GREEN: light = 3'b010;  // Green light on
            YELLOW: light = 3'b001; // Yellow light on
            default: light = 3'b100;
        endcase
    end

endmodule

This example uses a simple 3-state FSM: RED, GREEN, YELLOW.

The always @(posedge clk or posedge reset) block updates the current state.

Examples

Defines named states for clarity and easy state management.

Verilog

typedef enum reg [1:0] {RED=2'b00, GREEN=2'b01, YELLOW=2'b10} state_t;

Updates the current state on clock edge or resets to RED.

Verilog

always @(posedge clk or posedge reset) begin
    if (reset) state <= RED;
    else state <= next_state;
end

Decides the next state based on the current state.

Verilog

always @(*) begin
    case(state)
        RED: next_state = GREEN;
        GREEN: next_state = YELLOW;
        YELLOW: next_state = RED;
        default: next_state = RED;
    endcase
end

Sample Program

This program defines a traffic light FSM with three states. The testbench simulates clock and reset signals. The monitor prints the light output every time it changes.

Verilog

module traffic_light_fsm(
    input clk,
    input reset,
    output reg [2:0] light
);

    typedef enum reg [1:0] {
        RED = 2'b00,
        GREEN = 2'b01,
        YELLOW = 2'b10
    } state_t;

    state_t state, next_state;

    always @(posedge clk or posedge reset) begin
        if (reset) state <= RED;
        else state <= next_state;
    end

    always @(*) begin
        case(state)
            RED: next_state = GREEN;
            GREEN: next_state = YELLOW;
            YELLOW: next_state = RED;
            default: next_state = RED;
        endcase
    end

    always @(*) begin
        case(state)
            RED: light = 3'b100;
            GREEN: light = 3'b010;
            YELLOW: light = 3'b001;
            default: light = 3'b100;
        endcase
    end

endmodule

// Testbench to simulate the FSM
module testbench();
    reg clk = 0;
    reg reset = 1;
    wire [2:0] light;

    traffic_light_fsm fsm(.clk(clk), .reset(reset), .light(light));

    // Clock generation
    always #5 clk = ~clk;

    initial begin
        $monitor($time, " ns - Light: %b", light);
        #10 reset = 0; // Release reset after 10ns
        #100 $finish;
    end
endmodule

Important Notes

Use a testbench to simulate and verify your FSM behavior.

Each light is represented by a 3-bit code: red=100, green=010, yellow=001.

Resetting the FSM sets it to the RED state to start safely.

Summary

A traffic light FSM controls lights in a safe repeating order.

States and transitions are defined clearly using enums and case statements.

Testbenches help check the FSM works as expected before real use.