Up counter design in Verilog

Introduction

An up counter counts numbers in increasing order. It helps keep track of events or time in digital circuits.

Counting seconds in a digital clock

Tracking the number of items passing on a conveyor belt

Measuring how many times a button is pressed

Generating timed signals in a circuit

Syntax

Verilog

module up_counter(
    input clk,
    input reset,
    output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
    if (reset)
        count <= 4'b0000;
    else
        count <= count + 1;
end

endmodule

The posedge clk means the counter updates on the rising edge of the clock signal.

The reset input sets the counter back to zero when activated.

Examples

This example shows an 8-bit up counter that counts from 0 to 255.

Verilog

module up_counter_8bit(
    input clk,
    input reset,
    output reg [7:0] count
);

always @(posedge clk or posedge reset) begin
    if (reset)
        count <= 8'b00000000;
    else
        count <= count + 1;
end

endmodule

This counter only counts when the enable signal is high.

Verilog

module up_counter_with_enable(
    input clk,
    input reset,
    input enable,
    output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
    if (reset)
        count <= 4'b0000;
    else if (enable)
        count <= count + 1;
end

endmodule

Sample Program

This testbench runs the 4-bit up counter. It resets the counter first, then lets it count up every clock cycle. The monitor shows the count value over time.

Verilog

module testbench;
    reg clk = 0;
    reg reset = 1;
    wire [3:0] count;

    up_counter uut(
        .clk(clk),
        .reset(reset),
        .count(count)
    );

    always #5 clk = ~clk; // Clock toggles every 5 time units

    initial begin
        #10 reset = 0; // Release reset after 10 time units
        #100 $finish; // Stop simulation after 100 time units
    end

    initial begin
        $monitor("Time=%0t count=%b", $time, count);
    end
endmodule

Important Notes

Always use a reset signal to start the counter from a known value.

The counter width (number of bits) decides the maximum count value.

Clock signal must be stable and clean for correct counting.

Summary

An up counter increases its value on each clock pulse.

Use reset to set the counter back to zero.

You can add enable signals to control counting.