FSM with output logic in Verilog - Mini Project: Build & Apply

FSM with Output Logic in Verilog

📖 Scenario: You are designing a simple traffic light controller using a finite state machine (FSM). The traffic light cycles through three states: Green, Yellow, and Red. Each state lasts one clock cycle for simplicity.

🎯 Goal: Build a Verilog FSM that changes states on each clock cycle and outputs the correct light signal for each state.

📋 What You'll Learn

Create a state encoding using parameters

Use a register to hold the current state

Implement a synchronous state transition on the clock's rising edge

Add output logic that sets the traffic light signals based on the current state

Print the current state and output signals

💡 Why This Matters

🌍 Real World

Traffic light controllers use FSMs to manage light changes safely and predictably.

💼 Career

Understanding FSMs and output logic is essential for hardware design and embedded systems engineering.

1

Define the FSM states

Create three parameters called GREEN, YELLOW, and RED with values 2'b00, 2'b01, and 2'b10 respectively.

Verilog

// Your code here

Need a hint?

Use parameter keyword to define constant state values.

2

Create the state register and clock input

Declare a reg [1:0] state to hold the current state and an input clk for the clock signal.

Verilog

parameter GREEN = 2'b00;
parameter YELLOW = 2'b01;
parameter RED = 2'b10;

// Your code here

Need a hint?

Use reg [1:0] state; and input clk; declarations.

3

Implement the state transition logic

Write an always @(posedge clk) block that updates state to the next state in the sequence: GREEN → YELLOW → RED → GREEN.

Verilog

parameter GREEN = 2'b00;
parameter YELLOW = 2'b01;
parameter RED = 2'b10;

reg [1:0] state;
input clk;

// Your code here

Need a hint?

Use a case statement inside the always @(posedge clk) block to update state.

4

Add output logic and display the state

Declare three output wires green_light, yellow_light, and red_light. Assign them to 1 when state matches their color, else 0. Then, add a initial block to print the current state and output signals.

Verilog

parameter GREEN = 2'b00;
parameter YELLOW = 2'b01;
parameter RED = 2'b10;

reg [1:0] state;
input clk;

always @(posedge clk) begin
    case (state)
        GREEN: state <= YELLOW;
        YELLOW: state <= RED;
        RED: state <= GREEN;
        default: state <= GREEN;
    endcase
end

// Your code here

Need a hint?

Use conditional assignments for outputs and $monitor to print values.