Why FSMs model sequential behavior in Verilog

Introduction

FSMs (Finite State Machines) help us design circuits that remember past actions and decide what to do next step by step.

When you want a circuit to follow a set of steps in order, like a traffic light controller.

When you need to remember previous inputs to decide the next output, like a vending machine.

When designing digital systems that react differently based on history, such as a password checker.

Syntax

Verilog

module fsm_example(input clk, input reset, input in, output reg out);
  typedef enum logic [1:0] {S0, S1, S2} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  always_comb begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S2 : S0;
      S2: next_state = S0;
      default: next_state = S0;
    endcase
  end

  always_comb begin
    case(state)
      S0: out = 0;
      S1: out = 1;
      S2: out = 0;
      default: out = 0;
    endcase
  end
endmodule

This example shows a simple FSM with three states.

States change on clock edges, showing sequential behavior.

Examples

Defines states for the FSM using an enum for clarity.

Verilog

typedef enum logic [1:0] {IDLE, WORK, DONE} state_t;
state_t state, next_state;

Updates the current state on each clock cycle or resets it.

Verilog

always_ff @(posedge clk or posedge reset) begin
  if (reset)
    state <= IDLE;
  else
    state <= next_state;
end

Determines the next state based on the current state.

Verilog

always_comb begin
  case(state)
    IDLE: next_state = WORK;
    WORK: next_state = DONE;
    DONE: next_state = IDLE;
    default: next_state = IDLE;
  endcase
end

Sample Program

This program shows a simple FSM that changes states based on input and clock. The testbench runs the FSM and prints the current state and output over time.

Verilog

module simple_fsm(input clk, input reset, input in, output reg out);
  typedef enum logic [1:0] {S0, S1, S2} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  always_comb begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S2 : S0;
      S2: next_state = S0;
      default: next_state = S0;
    endcase
  end

  always_comb begin
    case(state)
      S0: out = 0;
      S1: out = 1;
      S2: out = 0;
      default: out = 0;
    endcase
  end
endmodule

// Testbench
module testbench();
  reg clk = 0;
  reg reset = 1;
  reg in = 0;
  wire out;

  simple_fsm fsm(clk, reset, in, out);

  always #5 clk = ~clk; // Clock toggles every 5 time units

  initial begin
    $display("Time State Out");
    $monitor("%0t %b %b", $time, fsm.state, out);

    #10 reset = 0; // Release reset
    #10 in = 1;    // Input high
    #10 in = 1;    // Input high
    #10 in = 0;    // Input low
    #20 $finish;
  end
endmodule

Important Notes

FSMs remember past states, so they model sequential steps, not just immediate inputs.

Using clock edges ensures changes happen in order, like steps in a recipe.

Resetting the FSM sets it back to a known starting point.

Summary

FSMs help circuits follow steps in order by remembering past states.

They change states on clock signals, showing sequential behavior.

This makes FSMs perfect for controlling processes that depend on history.