Moore machine vs Mealy machine in Verilog

Introduction

Moore and Mealy machines are ways to design circuits that remember past inputs and decide outputs. They help build simple decision-making hardware.

When you want a circuit that changes output only on clock edges (Moore).

When you want output to change immediately with input changes (Mealy).

When designing digital controllers or sequence detectors.

When you need predictable timing for outputs (Moore).

When you want faster response to inputs (Mealy).

Syntax

Verilog

module moore_machine(input clk, input reset, input in, output reg out);
  reg [1:0] state, next_state;

  // State encoding
  parameter S0 = 2'b00, S1 = 2'b01;

  // State transition
  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end

  // Next state logic
  always @(*) begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S1 : S0;
      default: next_state = S0;
    endcase
  end

  // Output logic depends only on state
  always @(*) begin
    case(state)
      S0: out = 0;
      S1: out = 1;
      default: out = 0;
    endcase
  end
endmodule

Moore machine output depends only on the current state.

Mealy machine output depends on current state and input.

Examples

This Mealy machine changes output immediately based on input and state.

Verilog

module mealy_machine(input clk, input reset, input in, output reg out);
  reg [1:0] state, next_state;

  parameter S0 = 2'b00, S1 = 2'b01;

  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end

  always @(*) begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S1 : S0;
      default: next_state = S0;
    endcase
  end

  // Output depends on state and input
  always @(*) begin
    case(state)
      S0: out = in;
      S1: out = ~in;
      default: out = 0;
    endcase
  end
endmodule

Simple Moore machine where output equals the current state.

Verilog

module moore_simple(input clk, input reset, input in, output reg out);
  reg state;

  always @(posedge clk or posedge reset) begin
    if (reset) state <= 0;
    else state <= in;
  end

  always @(*) begin
    out = state;
  end
endmodule

Sample Program

This testbench runs both Moore and Mealy machines with the same inputs. It shows how Moore output changes only on clock edges, while Mealy output can change immediately with input.

Verilog

module testbench();
  reg clk = 0;
  reg reset;
  reg in;
  wire out_moore, out_mealy;

  // Clock generation
  always #5 clk = ~clk;

  // Instantiate Moore machine
  moore_machine moore(clk, reset, in, out_moore);

  // Instantiate Mealy machine
  mealy_machine mealy(clk, reset, in, out_mealy);

  initial begin
    $monitor($time, " reset=%b in=%b Moore_out=%b Mealy_out=%b", reset, in, out_moore, out_mealy);
    reset = 1; in = 0;
    #10 reset = 0;
    #10 in = 1;
    #10 in = 0;
    #10 in = 1;
    #10 in = 0;
    #10 $finish;
  end
endmodule

module moore_machine(input clk, input reset, input in, output reg out);
  reg [1:0] state, next_state;
  parameter S0 = 2'b00, S1 = 2'b01;
  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end
  always @(*) begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S1 : S0;
      default: next_state = S0;
    endcase
  end
  always @(*) begin
    case(state)
      S0: out = 0;
      S1: out = 1;
      default: out = 0;
    endcase
  end
endmodule

module mealy_machine(input clk, input reset, input in, output reg out);
  reg [1:0] state, next_state;
  parameter S0 = 2'b00, S1 = 2'b01;
  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end
  always @(*) begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S1 : S0;
      default: next_state = S0;
    endcase
  end
  always @(*) begin
    case(state)
      S0: out = in;
      S1: out = ~in;
      default: out = 0;
    endcase
  end
endmodule

Important Notes

Moore machines are easier to design because output depends only on state.

Mealy machines can react faster but outputs may glitch if inputs change quickly.

In Verilog, use separate always blocks for state update, next state logic, and output logic for clarity.

Summary

Moore machine output depends only on the current state.

Mealy machine output depends on current state and input.

Moore outputs change on clock edges; Mealy outputs can change immediately with inputs.

Practice

1. Which statement correctly describes the output behavior of a Moore machine compared to a Mealy machine?

easy

A. Moore machine output depends only on the current state, while Mealy machine output depends on state and input.

B. Moore machine output depends on input only, Mealy machine output depends on current state only.

C. Both Moore and Mealy machines output depend only on the current input.

D. Moore machine output changes immediately with input, Mealy output changes only on clock edges.

Solution

1. Step 1: Understand Moore machine output dependency

   Moore machine outputs depend solely on the current state, not directly on inputs.

2. Step 2: Understand Mealy machine output dependency

   Mealy machine outputs depend on both the current state and the current input, allowing immediate output changes.

3. Final Answer:

   Moore machine output depends only on the current state, while Mealy machine output depends on state and input. -> Option A

4. Quick Check:

   Moore = state-only output, Mealy = state + input output [OK]

Hint: Moore = state only; Mealy = state plus input [OK]

Common Mistakes:

• Confusing output dependency on input for Moore machine
• Thinking Mealy output changes only on clock edges
• Assuming both machines output depend only on input

2. Which Verilog code snippet correctly models a Moore machine output?

easy

A. always @(input or state) output = input & state;

B. always @(posedge clk) output <= state;

C. always @(posedge clk or input) output <= input;

D. always @(input) output = state;

Solution

1. Step 1: Identify Moore machine output timing

   Moore machine outputs update only on clock edges, so output assignment must be inside a posedge clk block.

2. Step 2: Check code snippets for correct output assignment

   always @(posedge clk) output <= state; uses 'always @(posedge clk)' and assigns output from state, matching Moore behavior.

3. Final Answer:

   always @(posedge clk) output <= state; -> Option B

4. Quick Check:

   Moore output updates on clock edge only [OK]

Hint: Moore output inside posedge clk block [OK]

Common Mistakes:

• Using input sensitivity in Moore output block
• Assigning output directly from input in Moore machine
• Using combinational always block for Moore output

3. Given the following Verilog snippet for a Mealy machine output, what is the output when state = 1 and input = 0?

always @(state or input) begin
  if (state == 1)
    output = input;
  else
    output = 1;
end

medium

A. 1

B. Undefined

C. 0

D. Z (high impedance)

Solution

1. Step 1: Analyze condition when state = 1

   The if condition 'state == 1' is true, so output = input.

2. Step 2: Substitute input value

   Input is 0, so output = 0.

3. Final Answer:

   0 -> Option C

4. Quick Check:

   Mealy output depends on state and input, output = 0 [OK]

Hint: Check state condition first, then assign output [OK]

Common Mistakes:

• Ignoring input value when state is 1
• Assuming output is always 1
• Confusing Mealy output with Moore output

4. Identify the error in this Verilog code snippet intended to model a Moore machine output:

always @(input or state) begin
  output = state;
end

medium

A. Output assignment should use non-blocking '<=' operator.

B. Output should depend on input, not state.

C. The sensitivity list should include only input, not state.

D. Output should be assigned only on clock edge, not on input or state changes.

Solution

1. Step 1: Recall Moore machine output timing

   Moore machine outputs update only on clock edges, not on input or state changes directly.

2. Step 2: Check sensitivity list and assignment timing

   The sensitivity list includes input and state, causing output to update asynchronously, which is incorrect for Moore.

3. Final Answer:

   Output should be assigned only on clock edge, not on input or state changes. -> Option D

4. Quick Check:

   Moore output updates on clock edge only [OK]

Hint: Moore output must update only on clock edge [OK]

Common Mistakes:

• Using combinational always block for Moore output
• Ignoring clock in sensitivity list
• Confusing blocking and non-blocking assignments

5. You want to design a state machine in Verilog where the output must change immediately when the input changes, but also depend on the current state. Which machine type should you choose and why?

hard

A. Mealy machine, because output depends on state and input and can change immediately.

B. Moore machine, because it is simpler to implement and faster to respond.

C. Moore machine, because output depends only on state and changes on clock edges.

D. Neither, because outputs cannot depend on inputs in state machines.

Solution

1. Step 1: Understand output timing requirements

   The output must change immediately when input changes, so it cannot wait for clock edges.

2. Step 2: Match machine type to output behavior

   Mealy machine outputs depend on both state and input and can change immediately with input changes, fitting the requirement.

3. Final Answer:

   Mealy machine, because output depends on state and input and can change immediately. -> Option A

4. Quick Check:

   Immediate output change with input = Mealy machine [OK]

Hint: Immediate output change with input means Mealy machine [OK]

Common Mistakes:

• Choosing Moore machine for immediate output change
• Thinking Moore machine outputs depend on input
• Believing outputs cannot depend on inputs in state machines