Moore machine vs Mealy machine in Verilog

Introduction

Moore and Mealy machines are ways to design circuits that remember past inputs and decide outputs. They help build simple decision-making hardware.

When you want a circuit that changes output only on clock edges (Moore).

When you want output to change immediately with input changes (Mealy).

When designing digital controllers or sequence detectors.

When you need predictable timing for outputs (Moore).

When you want faster response to inputs (Mealy).

Syntax

Verilog

module moore_machine(input clk, input reset, input in, output reg out);
  reg [1:0] state, next_state;

  // State encoding
  parameter S0 = 2'b00, S1 = 2'b01;

  // State transition
  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end

  // Next state logic
  always @(*) begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S1 : S0;
      default: next_state = S0;
    endcase
  end

  // Output logic depends only on state
  always @(*) begin
    case(state)
      S0: out = 0;
      S1: out = 1;
      default: out = 0;
    endcase
  end
endmodule

Moore machine output depends only on the current state.

Mealy machine output depends on current state and input.

Examples

This Mealy machine changes output immediately based on input and state.

Verilog

module mealy_machine(input clk, input reset, input in, output reg out);
  reg [1:0] state, next_state;

  parameter S0 = 2'b00, S1 = 2'b01;

  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end

  always @(*) begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S1 : S0;
      default: next_state = S0;
    endcase
  end

  // Output depends on state and input
  always @(*) begin
    case(state)
      S0: out = in;
      S1: out = ~in;
      default: out = 0;
    endcase
  end
endmodule

Simple Moore machine where output equals the current state.

Verilog

module moore_simple(input clk, input reset, input in, output reg out);
  reg state;

  always @(posedge clk or posedge reset) begin
    if (reset) state <= 0;
    else state <= in;
  end

  always @(*) begin
    out = state;
  end
endmodule

Sample Program

This testbench runs both Moore and Mealy machines with the same inputs. It shows how Moore output changes only on clock edges, while Mealy output can change immediately with input.

Verilog

module testbench();
  reg clk = 0;
  reg reset;
  reg in;
  wire out_moore, out_mealy;

  // Clock generation
  always #5 clk = ~clk;

  // Instantiate Moore machine
  moore_machine moore(clk, reset, in, out_moore);

  // Instantiate Mealy machine
  mealy_machine mealy(clk, reset, in, out_mealy);

  initial begin
    $monitor($time, " reset=%b in=%b Moore_out=%b Mealy_out=%b", reset, in, out_moore, out_mealy);
    reset = 1; in = 0;
    #10 reset = 0;
    #10 in = 1;
    #10 in = 0;
    #10 in = 1;
    #10 in = 0;
    #10 $finish;
  end
endmodule

module moore_machine(input clk, input reset, input in, output reg out);
  reg [1:0] state, next_state;
  parameter S0 = 2'b00, S1 = 2'b01;
  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end
  always @(*) begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S1 : S0;
      default: next_state = S0;
    endcase
  end
  always @(*) begin
    case(state)
      S0: out = 0;
      S1: out = 1;
      default: out = 0;
    endcase
  end
endmodule

module mealy_machine(input clk, input reset, input in, output reg out);
  reg [1:0] state, next_state;
  parameter S0 = 2'b00, S1 = 2'b01;
  always @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end
  always @(*) begin
    case(state)
      S0: next_state = in ? S1 : S0;
      S1: next_state = in ? S1 : S0;
      default: next_state = S0;
    endcase
  end
  always @(*) begin
    case(state)
      S0: out = in;
      S1: out = ~in;
      default: out = 0;
    endcase
  end
endmodule

Important Notes

Moore machines are easier to design because output depends only on state.

Mealy machines can react faster but outputs may glitch if inputs change quickly.

In Verilog, use separate always blocks for state update, next state logic, and output logic for clarity.

Summary

Moore machine output depends only on the current state.

Mealy machine output depends on current state and input.

Moore outputs change on clock edges; Mealy outputs can change immediately with inputs.