FSM with output logic in Verilog

Introduction

An FSM (Finite State Machine) with output logic helps control devices by changing states and producing outputs based on inputs and current state.

Controlling a traffic light system that changes lights and signals.

Designing a vending machine that gives products and change.

Managing a simple elevator control system with floor indicators.

Creating a digital lock that outputs signals when unlocked.

Syntax

Verilog

module fsm_with_output(
    input clk,
    input reset,
    input in_signal,
    output reg out_signal
);

    typedef enum logic [1:0] {
        S0 = 2'b00,
        S1 = 2'b01,
        S2 = 2'b10
    } state_t;

    state_t current_state, next_state;

    // State transition logic
    always_ff @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= S0;
        else
            current_state <= next_state;
    end

    // Next state logic
    always_comb begin
        case (current_state)
            S0: next_state = in_signal ? S1 : S0;
            S1: next_state = in_signal ? S2 : S0;
            S2: next_state = S0;
            default: next_state = S0;
        endcase
    end

    // Output logic
    always_comb begin
        case (current_state)
            S0: out_signal = 0;
            S1: out_signal = 1;
            S2: out_signal = 1;
            default: out_signal = 0;
        endcase
    end

endmodule

The FSM has three parts: state register, next state logic, and output logic.

Output logic can be Moore style (depends only on state) or Mealy style (depends on state and input). This example uses Moore style.

Examples

Defines states using an enum for clarity and easier state management.

Verilog

typedef enum logic [1:0] {S0 = 2'b00, S1 = 2'b01} state_t;

state_t current_state, next_state;

Registers the current state on clock edge and resets to initial state.

Verilog

always_ff @(posedge clk or posedge reset) begin
    if (reset)
        current_state <= S0;
    else
        current_state <= next_state;
end

Determines the next state based on current state and input signal.

Verilog

always_comb begin
    case (current_state)
        S0: next_state = in_signal ? S1 : S0;
        S1: next_state = S0;
        default: next_state = S0;
    endcase
end

Sets output based only on the current state (Moore output logic).

Verilog

always_comb begin
    case (current_state)
        S0: out_signal = 0;
        S1: out_signal = 1;
        default: out_signal = 0;
    endcase
end

Sample Program

This example shows a simple FSM with three states and output logic. The testbench simulates input signals and prints the output at each clock cycle.

Verilog

module fsm_with_output(
    input clk,
    input reset,
    input in_signal,
    output reg out_signal
);

    typedef enum logic [1:0] {
        S0 = 2'b00,
        S1 = 2'b01,
        S2 = 2'b10
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= S0;
        else
            current_state <= next_state;
    end

    always_comb begin
        case (current_state)
            S0: next_state = in_signal ? S1 : S0;
            S1: next_state = in_signal ? S2 : S0;
            S2: next_state = S0;
            default: next_state = S0;
        endcase
    end

    always_comb begin
        case (current_state)
            S0: out_signal = 0;
            S1: out_signal = 1;
            S2: out_signal = 1;
            default: out_signal = 0;
        endcase
    end

endmodule

// Testbench to simulate the FSM
module testbench();
    logic clk = 0;
    logic reset;
    logic in_signal;
    logic out_signal;

    fsm_with_output fsm(.clk(clk), .reset(reset), .in_signal(in_signal), .out_signal(out_signal));

    always #5 clk = ~clk; // Clock toggles every 5 time units

    initial begin
        $display("Time Reset In_signal Out_signal");
        reset = 1; in_signal = 0;
        #10 reset = 0;

        #10 in_signal = 1; // Move from S0 to S1
        #10 in_signal = 1; // Move from S1 to S2
        #10 in_signal = 0; // Move from S2 to S0
        #10 in_signal = 1; // Move from S0 to S1
        #10 in_signal = 0; // Move from S1 to S0

        #20 $finish;
    end

    always @(posedge clk) begin
        $display("%0t    %b     %b        %b", $time, reset, in_signal, out_signal);
    end
endmodule

Important Notes

Use always_ff for sequential logic (state updates) and always_comb for combinational logic (next state and output).

Resetting the FSM ensures it starts in a known state.

Output logic can be changed to Mealy style by including inputs in the output logic block.

Summary

An FSM with output logic controls outputs based on states.

Use separate blocks for state update, next state logic, and output logic.

Moore outputs depend only on the current state, making timing simpler.