FSM with output logic in Verilog

Introduction

An FSM (Finite State Machine) with output logic helps control devices by changing states and producing outputs based on inputs and current state.

Controlling a traffic light system that changes lights and signals.

Designing a vending machine that gives products and change.

Managing a simple elevator control system with floor indicators.

Creating a digital lock that outputs signals when unlocked.

Syntax

Verilog

module fsm_with_output(
    input clk,
    input reset,
    input in_signal,
    output reg out_signal
);

    typedef enum logic [1:0] {
        S0 = 2'b00,
        S1 = 2'b01,
        S2 = 2'b10
    } state_t;

    state_t current_state, next_state;

    // State transition logic
    always_ff @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= S0;
        else
            current_state <= next_state;
    end

    // Next state logic
    always_comb begin
        case (current_state)
            S0: next_state = in_signal ? S1 : S0;
            S1: next_state = in_signal ? S2 : S0;
            S2: next_state = S0;
            default: next_state = S0;
        endcase
    end

    // Output logic
    always_comb begin
        case (current_state)
            S0: out_signal = 0;
            S1: out_signal = 1;
            S2: out_signal = 1;
            default: out_signal = 0;
        endcase
    end

endmodule

The FSM has three parts: state register, next state logic, and output logic.

Output logic can be Moore style (depends only on state) or Mealy style (depends on state and input). This example uses Moore style.

Examples

Defines states using an enum for clarity and easier state management.

Verilog

typedef enum logic [1:0] {S0 = 2'b00, S1 = 2'b01} state_t;

state_t current_state, next_state;

Registers the current state on clock edge and resets to initial state.

Verilog

always_ff @(posedge clk or posedge reset) begin
    if (reset)
        current_state <= S0;
    else
        current_state <= next_state;
end

Determines the next state based on current state and input signal.

Verilog

always_comb begin
    case (current_state)
        S0: next_state = in_signal ? S1 : S0;
        S1: next_state = S0;
        default: next_state = S0;
    endcase
end

Sets output based only on the current state (Moore output logic).

Verilog

always_comb begin
    case (current_state)
        S0: out_signal = 0;
        S1: out_signal = 1;
        default: out_signal = 0;
    endcase
end

Sample Program

This example shows a simple FSM with three states and output logic. The testbench simulates input signals and prints the output at each clock cycle.

Verilog

module fsm_with_output(
    input clk,
    input reset,
    input in_signal,
    output reg out_signal
);

    typedef enum logic [1:0] {
        S0 = 2'b00,
        S1 = 2'b01,
        S2 = 2'b10
    } state_t;

    state_t current_state, next_state;

    always_ff @(posedge clk or posedge reset) begin
        if (reset)
            current_state <= S0;
        else
            current_state <= next_state;
    end

    always_comb begin
        case (current_state)
            S0: next_state = in_signal ? S1 : S0;
            S1: next_state = in_signal ? S2 : S0;
            S2: next_state = S0;
            default: next_state = S0;
        endcase
    end

    always_comb begin
        case (current_state)
            S0: out_signal = 0;
            S1: out_signal = 1;
            S2: out_signal = 1;
            default: out_signal = 0;
        endcase
    end

endmodule

// Testbench to simulate the FSM
module testbench();
    logic clk = 0;
    logic reset;
    logic in_signal;
    logic out_signal;

    fsm_with_output fsm(.clk(clk), .reset(reset), .in_signal(in_signal), .out_signal(out_signal));

    always #5 clk = ~clk; // Clock toggles every 5 time units

    initial begin
        $display("Time Reset In_signal Out_signal");
        reset = 1; in_signal = 0;
        #10 reset = 0;

        #10 in_signal = 1; // Move from S0 to S1
        #10 in_signal = 1; // Move from S1 to S2
        #10 in_signal = 0; // Move from S2 to S0
        #10 in_signal = 1; // Move from S0 to S1
        #10 in_signal = 0; // Move from S1 to S0

        #20 $finish;
    end

    always @(posedge clk) begin
        $display("%0t    %b     %b        %b", $time, reset, in_signal, out_signal);
    end
endmodule

Important Notes

Use always_ff for sequential logic (state updates) and always_comb for combinational logic (next state and output).

Resetting the FSM ensures it starts in a known state.

Output logic can be changed to Mealy style by including inputs in the output logic block.

Summary

An FSM with output logic controls outputs based on states.

Use separate blocks for state update, next state logic, and output logic.

Moore outputs depend only on the current state, making timing simpler.

Practice

1. Which part of an FSM with output logic determines the output signals based only on the current state?

easy

A. Input decoder

B. Next state logic

C. State register

D. Output logic in a Moore machine

Solution

1. Step 1: Understand FSM output types

   In FSMs, Moore outputs depend only on the current state, while Mealy outputs depend on state and input.

2. Step 2: Identify output logic role

   The output logic in a Moore machine produces outputs based solely on the current state stored in the state register.

3. Final Answer:

   Output logic in a Moore machine -> Option D

4. Quick Check:

   Moore output = state only [OK]

Hint: Moore outputs depend only on state, not inputs [OK]

Common Mistakes:

• Confusing next state logic with output logic
• Thinking outputs depend on inputs in Moore FSM
• Mixing state register role with output logic

2. Which of the following is the correct Verilog syntax to declare a state register named state with 2 bits?

easy

A. reg [1:0] state;

B. wire [2:0] state;

C. reg state[1:0];

D. state reg [1:0];

Solution

1. Step 1: Recall Verilog register declaration

   Registers are declared with reg keyword followed by bit width in brackets, e.g., reg [1:0] for 2 bits.

2. Step 2: Check each option

   reg [1:0] state; correctly declares a 2-bit register named state. wire [2:0] state; uses wire and wrong width. reg state[1:0]; uses incorrect syntax for bit width. state reg [1:0]; has wrong keyword order.

3. Final Answer:

   reg [1:0] state; -> Option A

4. Quick Check:

   reg [1:0] state; is correct syntax [OK]

Hint: Use reg [width-1:0] name; for registers [OK]

Common Mistakes:

• Using wire instead of reg for state registers
• Incorrect bit width syntax like reg name[1:0]
• Wrong keyword order like state reg

3. Given this Verilog snippet for a Moore FSM output logic:

always @(state) begin
  case(state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    2'b10: out = 1'b0;
    default: out = 1'b0;
  endcase
end

What is the output out when state is 2'b01?

medium

A. 1'b0

B. Undefined

C. 1'b1

D. 2'b01

Solution

1. Step 1: Check case for state 2'b01

   The case statement sets out = 1'b1 when state is 2'b01.

2. Step 2: Confirm output value

   Since the state matches 2'b01, output out is assigned 1'b1.

3. Final Answer:

   1'b1 -> Option C

4. Quick Check:

   State 01 -> out = 1 [OK]

Hint: Match state in case to find output quickly [OK]

Common Mistakes:

• Confusing output with state value
• Assuming default applies instead of matching case
• Misreading bit values as decimal

4. Identify the error in this FSM output logic code snippet:

always @(posedge clk) begin
  case(state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    default: out = 1'b0;
  endcase
end

What is the main problem?

medium

A. Output logic should be in a combinational always block, not clocked

B. Missing reset signal for output

C. State values are incorrectly formatted

D. Output out is not declared as reg

Solution

1. Step 1: Understand output logic timing

   Moore FSM output logic is usually combinational and depends only on state, so it should be in an always block sensitive to state changes, not clock edges.

2. Step 2: Analyze given code

   The code uses always @(posedge clk), making output synchronous, which is incorrect for pure output logic in Moore FSM.

3. Final Answer:

   Output logic should be in a combinational always block, not clocked -> Option A

4. Quick Check:

   Output logic = combinational, not clocked [OK]

Hint: Output logic usually uses always @(*) for combinational [OK]

Common Mistakes:

• Using clocked always block for output logic
• Ignoring sensitivity list correctness
• Confusing output and state update blocks

5. You want to design a Mealy FSM with output logic that sets out = 1 only when the current state is 2'b10 and input in is high. Which Verilog code snippet correctly implements this output logic?

hard

A. always @(in) begin\n if (in)\n out = 1'b1;\n else\n out = 1'b0;\nend

B. always @(state or in) begin\n if (state == 2'b10 && in)\n out = 1'b1;\n else\n out = 1'b0;\nend

C. always @(posedge clk) begin\n if (state == 2'b10 && in)\n out <= 1'b1;\n else\n out <= 1'b0;\nend

D. always @(state) begin\n if (state == 2'b10)\n out = 1'b1;\n else\n out = 1'b0;\nend

Solution

1. Step 1: Understand Mealy output logic

   Mealy outputs depend on both current state and inputs, so sensitivity list must include both state and in.

2. Step 2: Check each option

   always @(state or in) begin\n if (state == 2'b10 && in)\n out = 1'b1;\n else\n out = 1'b0;\nend correctly uses always @(state or in) and sets out based on both conditions. always @(state) begin\n if (state == 2'b10)\n out = 1'b1;\n else\n out = 1'b0;\nend ignores input in. always @(posedge clk) begin\n if (state == 2'b10 && in)\n out <= 1'b1;\n else\n out <= 1'b0;\nend uses clocked block which is not typical for Mealy output logic. always @(in) begin\n if (in)\n out = 1'b1;\n else\n out = 1'b0;\nend ignores state.

3. Final Answer:

   always @(state or in) begin if (state == 2'b10 && in) out = 1'b1; else out = 1'b0; end -> Option B

4. Quick Check:

   Mealy output depends on state and input [OK]

Hint: Include both state and input in sensitivity list for Mealy outputs [OK]

Common Mistakes:

• Leaving input out of sensitivity list
• Using clocked always block for Mealy output
• Ignoring state condition in output logic