FSM with output logic in Verilog - Time & Space Complexity

Time Complexity: FSM with output logic

O(n)

Understanding Time Complexity

We want to understand how the time it takes to run a finite state machine (FSM) with output logic changes as the input size or clock cycles increase.

Specifically, we ask: how does the number of operations grow as the FSM processes more inputs?

Scenario Under Consideration

Analyze the time complexity of the following code snippet.

module fsm_with_output(
  input clk, reset, in,
  output reg out
);
  typedef enum logic [1:0] {S0, S1, S2} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge reset) begin
    if (reset) state <= S0;
    else state <= next_state;
  end

  always_comb begin
    case(state)
      S0: begin
        out = 0;
        next_state = in ? S1 : S0;
      end
      S1: begin
        out = 1;
        next_state = in ? S2 : S0;
      end
      S2: begin
        out = 0;
        next_state = in ? S2 : S0;
      end
    endcase
  end
endmodule

This code models a simple FSM with three states and output logic based on the current state and input.

Identify Repeating Operations

Identify the loops, recursion, array traversals that repeat.

• Primary operation: The FSM updates its state on every clock cycle.
• How many times: Once per clock cycle, repeating indefinitely as inputs arrive.

How Execution Grows With Input

Each clock cycle causes the FSM to evaluate its current state and input, then update its state and output.

Input Size (clock cycles)	Approx. Operations
10	10 state updates and output calculations
100	100 state updates and output calculations
1000	1000 state updates and output calculations

Pattern observation: The number of operations grows linearly with the number of clock cycles processed.

Final Time Complexity

Time Complexity: O(n)

This means the time to process inputs grows directly in proportion to the number of clock cycles.

Common Mistake

[X] Wrong: "The FSM processes all inputs instantly regardless of input length."

[OK] Correct: Each input requires a clock cycle to update the state and output, so processing time grows with input length.

Interview Connect

Understanding how FSMs scale with input size helps you design efficient hardware and explain timing behavior clearly in interviews.

Self-Check

"What if the FSM had nested loops inside the output logic? How would the time complexity change?"

Practice

1. Which part of an FSM with output logic determines the output signals based only on the current state?

easy

A. Input decoder

B. Next state logic

C. State register

D. Output logic in a Moore machine

Solution

1. Step 1: Understand FSM output types

   In FSMs, Moore outputs depend only on the current state, while Mealy outputs depend on state and input.

2. Step 2: Identify output logic role

   The output logic in a Moore machine produces outputs based solely on the current state stored in the state register.

3. Final Answer:

   Output logic in a Moore machine -> Option D

4. Quick Check:

   Moore output = state only [OK]

Hint: Moore outputs depend only on state, not inputs [OK]

Common Mistakes:

• Confusing next state logic with output logic
• Thinking outputs depend on inputs in Moore FSM
• Mixing state register role with output logic

2. Which of the following is the correct Verilog syntax to declare a state register named state with 2 bits?

easy

A. reg [1:0] state;

B. wire [2:0] state;

C. reg state[1:0];

D. state reg [1:0];

Solution

1. Step 1: Recall Verilog register declaration

   Registers are declared with reg keyword followed by bit width in brackets, e.g., reg [1:0] for 2 bits.

2. Step 2: Check each option

   reg [1:0] state; correctly declares a 2-bit register named state. wire [2:0] state; uses wire and wrong width. reg state[1:0]; uses incorrect syntax for bit width. state reg [1:0]; has wrong keyword order.

3. Final Answer:

   reg [1:0] state; -> Option A

4. Quick Check:

   reg [1:0] state; is correct syntax [OK]

Hint: Use reg [width-1:0] name; for registers [OK]

Common Mistakes:

• Using wire instead of reg for state registers
• Incorrect bit width syntax like reg name[1:0]
• Wrong keyword order like state reg

3. Given this Verilog snippet for a Moore FSM output logic:

always @(state) begin
  case(state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    2'b10: out = 1'b0;
    default: out = 1'b0;
  endcase
end

What is the output out when state is 2'b01?

medium

A. 1'b0

B. Undefined

C. 1'b1

D. 2'b01

Solution

1. Step 1: Check case for state 2'b01

   The case statement sets out = 1'b1 when state is 2'b01.

2. Step 2: Confirm output value

   Since the state matches 2'b01, output out is assigned 1'b1.

3. Final Answer:

   1'b1 -> Option C

4. Quick Check:

   State 01 -> out = 1 [OK]

Hint: Match state in case to find output quickly [OK]

Common Mistakes:

• Confusing output with state value
• Assuming default applies instead of matching case
• Misreading bit values as decimal

4. Identify the error in this FSM output logic code snippet:

always @(posedge clk) begin
  case(state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    default: out = 1'b0;
  endcase
end

What is the main problem?

medium

A. Output logic should be in a combinational always block, not clocked

B. Missing reset signal for output

C. State values are incorrectly formatted

D. Output out is not declared as reg

Solution

1. Step 1: Understand output logic timing

   Moore FSM output logic is usually combinational and depends only on state, so it should be in an always block sensitive to state changes, not clock edges.

2. Step 2: Analyze given code

   The code uses always @(posedge clk), making output synchronous, which is incorrect for pure output logic in Moore FSM.

3. Final Answer:

   Output logic should be in a combinational always block, not clocked -> Option A

4. Quick Check:

   Output logic = combinational, not clocked [OK]

Hint: Output logic usually uses always @(*) for combinational [OK]

Common Mistakes:

• Using clocked always block for output logic
• Ignoring sensitivity list correctness
• Confusing output and state update blocks

5. You want to design a Mealy FSM with output logic that sets out = 1 only when the current state is 2'b10 and input in is high. Which Verilog code snippet correctly implements this output logic?

hard

A. always @(in) begin\n if (in)\n out = 1'b1;\n else\n out = 1'b0;\nend

B. always @(state or in) begin\n if (state == 2'b10 && in)\n out = 1'b1;\n else\n out = 1'b0;\nend

C. always @(posedge clk) begin\n if (state == 2'b10 && in)\n out <= 1'b1;\n else\n out <= 1'b0;\nend

D. always @(state) begin\n if (state == 2'b10)\n out = 1'b1;\n else\n out = 1'b0;\nend

Solution

1. Step 1: Understand Mealy output logic

   Mealy outputs depend on both current state and inputs, so sensitivity list must include both state and in.

2. Step 2: Check each option

   always @(state or in) begin\n if (state == 2'b10 && in)\n out = 1'b1;\n else\n out = 1'b0;\nend correctly uses always @(state or in) and sets out based on both conditions. always @(state) begin\n if (state == 2'b10)\n out = 1'b1;\n else\n out = 1'b0;\nend ignores input in. always @(posedge clk) begin\n if (state == 2'b10 && in)\n out <= 1'b1;\n else\n out <= 1'b0;\nend uses clocked block which is not typical for Mealy output logic. always @(in) begin\n if (in)\n out = 1'b1;\n else\n out = 1'b0;\nend ignores state.

3. Final Answer:

   always @(state or in) begin if (state == 2'b10 && in) out = 1'b1; else out = 1'b0; end -> Option B

4. Quick Check:

   Mealy output depends on state and input [OK]

Hint: Include both state and input in sensitivity list for Mealy outputs [OK]

Common Mistakes:

• Leaving input out of sensitivity list
• Using clocked always block for Mealy output
• Ignoring state condition in output logic