FSM with output logic in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the state register.

Verilog

reg [1:0] [1];

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Ainput

Bstate

Coutput

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using input or output names instead of the state register.

The state register holds the current state of the FSM and is declared as state.

2fill in blank

medium

Complete the code to define the next state logic using a case statement.

Verilog

always @(*) begin
  case (state)
    2'b00: next_state = [1];
    default: next_state = 2'b00;
  endcase
end

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A2'b11

B2'b10

C2'b01

D2'b00

Attempts:

3 left

💡 Hint

Common Mistakes

Choosing the current state as next state causing no transition.

The next state after 2'b00 is 2'b01 as per the FSM design.

3fill in blank

hard

Fix the error in the output logic to assign output based on the current state.

Verilog

always @(*) begin
  case ([1])
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    default: out = 1'b0;
  endcase
end

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Anext_state

Bclk

Cinput

Dstate

Attempts:

3 left

💡 Hint

Common Mistakes

Using next_state or input signals instead of current state.

The output depends on the current state, not the next state or inputs.

4fill in blank

hard

Fill both blanks to complete the synchronous state update logic.

Verilog

always @(posedge [1] or posedge [2]) begin
  if (reset)
    state <= 2'b00;
  else
    state <= next_state;
end

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Aclk

Breset

Cinput

Dout

Attempts:

3 left

💡 Hint

Common Mistakes

Using input or output signals instead of clock or reset.

The state updates on the rising edge of the clock clk or asynchronous reset reset.

5fill in blank

hard

Fill all three blanks to complete the FSM module header and port declarations.

Verilog

module fsm(
  input wire [1],
  input wire [2],
  output reg [3]
);

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Aclk

Breset

Cout

Dstate

Attempts:

3 left

💡 Hint

Common Mistakes

Using internal signals like state as ports.

The FSM module has inputs clk and reset, and output out.