Always block sensitivity list in Verilog

Introduction

An always block sensitivity list tells Verilog when to run the code inside an always block. It helps the circuit react to changes in signals.

When you want to update outputs whenever certain inputs change.

When modeling combinational logic that depends on some signals.

When describing sequential logic that reacts to clock edges.

When you want to avoid running code unnecessarily to save simulation time.

Syntax

Verilog

always @(sensitivity_list) begin
    // statements
end

The sensitivity_list can include signals or edges like posedge clk or negedge reset.

If you want to model combinational logic, include all input signals in the sensitivity list.

Examples

This runs whenever a, b, or c changes. It models combinational AND logic.

Verilog

always @(a or b or c) begin
    y = a & b & c;
end

This runs only on the rising edge of clk. It models a flip-flop storing d.

Verilog

always @(posedge clk) begin
    q <= d;
end

This runs on clock rising edge or reset falling edge. It models a flip-flop with asynchronous reset.

Verilog

always @(posedge clk or negedge reset) begin
    if (!reset)
        q <= 0;
    else
        q <= d;
end

The @(*) means "all inputs used inside". It automatically includes all signals read inside the block.

Verilog

always @(*) begin
    y = a | b;
end

Sample Program

This example shows an always block sensitive to a and b. It updates y whenever a or b changes, modeling an AND gate.

Verilog

module simple_and(
    input wire a,
    input wire b,
    output reg y
);

always @(a or b) begin
    y = a & b;
end

endmodule

// Testbench
module testbench;
    reg a;
    reg b;
    wire y;

    simple_and uut(.a(a), .b(b), .y(y));

    initial begin
        a = 0; b = 0;
        #10 a = 1;
        #10 b = 1;
        #10 a = 0;
        #10 b = 0;
        #10 $finish;
    end

    initial begin
        $monitor($time, ": a=%b b=%b y=%b", a, b, y);
    end
endmodule

Important Notes

Time complexity: The always block runs only when signals in the sensitivity list change, making simulation efficient.

Space complexity: Minimal, just stores the signals and output.

Common mistake: Forgetting to include all input signals in the sensitivity list for combinational logic can cause simulation mismatches.

Use @(*) for combinational logic to avoid missing signals in the sensitivity list.

Summary

The always block sensitivity list controls when the block runs.

Use signal names or edges like posedge in the list.

Use @(*) to automatically include all inputs for combinational logic.

Practice

1. What does the sensitivity list in a Verilog always block control?

easy

A. The data type of variables inside the block

B. The clock frequency of the design

C. When the always block executes based on signal changes

D. The synthesis tool optimization level

Solution

1. Step 1: Understand the role of sensitivity list

   The sensitivity list specifies which signals trigger the always block to run when they change.

2. Step 2: Differentiate from unrelated concepts

   Data types, clock frequency, and synthesis optimization are unrelated to sensitivity lists.

3. Final Answer:

   When the always block executes based on signal changes -> Option C

4. Quick Check:

   Sensitivity list controls execution timing [OK]

Hint: Sensitivity list triggers block on signal changes [OK]

Common Mistakes:

• Confusing sensitivity list with clock frequency
• Thinking it controls variable types
• Assuming it affects synthesis optimization

2. Which of the following is the correct syntax for an always block sensitivity list that triggers on the positive edge of clock clk and any change in reset rst?

easy

A. always @(posedge clk and rst)

B. always @(posedge clk or rst)

C. always @(clk posedge or rst)

D. always @(posedge clk, rst)

Solution

1. Step 1: Recall correct sensitivity list syntax

   The correct syntax uses posedge clk and or to separate signals: always @(posedge clk or rst).

2. Step 2: Identify incorrect syntax in other options

   A uses and instead of or, B uses wrong order clk posedge, D uses comma which is invalid.

3. Final Answer:

   always @(posedge clk or rst) -> Option B

4. Quick Check:

   Use 'or' to separate signals in sensitivity list [OK]

Hint: Use 'or' between signals, 'posedge' before clock [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Placing 'posedge' after signal name
• Separating signals with commas

3. Consider the following Verilog code snippet:

reg q;
always @(posedge clk or posedge rst) begin
  if (rst)
    q <= 0;
  else
    q <= d;
end

What happens to q when rst goes high?

medium

A. q is set to 0 immediately

B. q holds its previous value

C. q is set to d

D. Synthesis error occurs

Solution

1. Step 1: Analyze sensitivity list triggers

   The block triggers on positive edge of clk or rst. When rst goes high, the block runs immediately.

2. Step 2: Check the if condition inside the block

   If rst is high, q is assigned 0, resetting it.

3. Final Answer:

   q is set to 0 immediately -> Option A

4. Quick Check:

   Reset high sets q to 0 [OK]

Hint: Reset in sensitivity list triggers immediate reset [OK]

Common Mistakes:

• Assuming q holds value on reset
• Thinking q updates only on clock edge
• Confusing reset with data input

4. Identify the error in this Verilog code:

always @(clk or rst) begin
  if (rst)
    q <= 0;
  else if (posedge clk)
    q <= d;
end

medium

A. No error, code is correct

B. Missing negedge rst in sensitivity list

C. Incorrect use of nonblocking assignment <=

D. Using posedge clk inside the block instead of sensitivity list

Solution

1. Step 1: Check sensitivity list correctness

   The sensitivity list uses clk and rst without edges, so it triggers on any change.

2. Step 2: Identify improper use of posedge clk inside block

   You cannot use posedge clk as a condition inside the block; it must be in sensitivity list.

3. Final Answer:

   Using posedge clk inside the block instead of sensitivity list -> Option D

4. Quick Check:

   Edge triggers belong in sensitivity list [OK]

Hint: Put edge triggers only in sensitivity list [OK]

Common Mistakes:

• Placing edge conditions inside always block
• Ignoring sensitivity list edges
• Confusing blocking and nonblocking assignments

5. You want to write a combinational logic block that updates output y whenever any input signal a, b, or c changes. Which sensitivity list is best practice to ensure correct behavior?

hard

A. always @(*)

B. always @(negedge a and negedge b and negedge c)

C. always @(posedge a or posedge b or posedge c)

D. always @(a or b or c)

Solution

1. Step 1: Understand combinational logic sensitivity

   For combinational logic, sensitivity list should include all inputs to avoid simulation mismatches.

2. Step 2: Use @(*) for automatic sensitivity

   @(*) automatically includes all signals read inside the block, ensuring correctness and easier maintenance.

3. Final Answer:

   always @(*) -> Option A

4. Quick Check:

   Use @(*) for combinational logic sensitivity [OK]

Hint: Use @(*) to cover all inputs automatically [OK]

Common Mistakes:

• Listing signals manually and missing some
• Using edge triggers for combinational logic
• Using 'and' instead of 'or' in sensitivity list