Always block sensitivity list in Verilog

Introduction

An always block sensitivity list tells Verilog when to run the code inside an always block. It helps the circuit react to changes in signals.

When you want to update outputs whenever certain inputs change.

When modeling combinational logic that depends on some signals.

When describing sequential logic that reacts to clock edges.

When you want to avoid running code unnecessarily to save simulation time.

Syntax

Verilog

always @(sensitivity_list) begin
    // statements
end

The sensitivity_list can include signals or edges like posedge clk or negedge reset.

If you want to model combinational logic, include all input signals in the sensitivity list.

Examples

This runs whenever a, b, or c changes. It models combinational AND logic.

Verilog

always @(a or b or c) begin
    y = a & b & c;
end

This runs only on the rising edge of clk. It models a flip-flop storing d.

Verilog

always @(posedge clk) begin
    q <= d;
end

This runs on clock rising edge or reset falling edge. It models a flip-flop with asynchronous reset.

Verilog

always @(posedge clk or negedge reset) begin
    if (!reset)
        q <= 0;
    else
        q <= d;
end

The @(*) means "all inputs used inside". It automatically includes all signals read inside the block.

Verilog

always @(*) begin
    y = a | b;
end

Sample Program

This example shows an always block sensitive to a and b. It updates y whenever a or b changes, modeling an AND gate.

Verilog

module simple_and(
    input wire a,
    input wire b,
    output reg y
);

always @(a or b) begin
    y = a & b;
end

endmodule

// Testbench
module testbench;
    reg a;
    reg b;
    wire y;

    simple_and uut(.a(a), .b(b), .y(y));

    initial begin
        a = 0; b = 0;
        #10 a = 1;
        #10 b = 1;
        #10 a = 0;
        #10 b = 0;
        #10 $finish;
    end

    initial begin
        $monitor($time, ": a=%b b=%b y=%b", a, b, y);
    end
endmodule

Important Notes

Time complexity: The always block runs only when signals in the sensitivity list change, making simulation efficient.

Space complexity: Minimal, just stores the signals and output.

Common mistake: Forgetting to include all input signals in the sensitivity list for combinational logic can cause simulation mismatches.

Use @(*) for combinational logic to avoid missing signals in the sensitivity list.

Summary

The always block sensitivity list controls when the block runs.

Use signal names or edges like posedge in the list.

Use @(*) to automatically include all inputs for combinational logic.