FSM with output logic in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a Moore FSM with two states

What is the output z after the FSM processes the input sequence 1, 0, 1?

The FSM has two states: S0 (output 0) and S1 (output 1). It starts in S0. On input 1, it moves from S0 to S1. On input 0, it moves from S1 to S0. Output depends only on the current state.

Verilog

module fsm_moore(input clk, input rst, input x, output reg z);
  typedef enum logic {S0, S1} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else state <= next_state;
  end

  always_comb begin
    case(state)
      S0: next_state = (x) ? S1 : S0;
      S1: next_state = (x) ? S1 : S0;
      default: next_state = S0;
    endcase
  end

  always_comb begin
    case(state)
      S0: z = 0;
      S1: z = 1;
      default: z = 0;
    endcase
  end
endmodule

A [1, 1, 1]

B [0, 0, 1]

C [0, 1, 1]

D [0, 1, 0]

💡 Hint

Remember, output depends only on the current state before input changes.

The FSM starts in S0 (z=0). Input 1: current S0 z=0, next S1. Input 0: current S1 z=1, next S0. Input 1: current S0 z=0, next S1. Output sequence [0,1,0].

❓ Predict Output

intermediate

Output of a Mealy FSM with output on transitions

What is the output z sequence for input 1, 0, 1 on this Mealy FSM?

The FSM has states S0 and S1. It starts in S0. Output z depends on current state and input.

Verilog

module fsm_mealy(input clk, input rst, input x, output reg z);
  typedef enum logic {S0, S1} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else state <= next_state;
  end

  always_comb begin
    case(state)
      S0: begin
        z = x;
        next_state = (x) ? S1 : S0;
      end
      S1: begin
        z = ~x;
        next_state = (x) ? S1 : S0;
      end
      default: begin
        z = 0;
        next_state = S0;
      end
    endcase
  end
endmodule

A [1, 1, 1]

B [0, 1, 0]

C [1, 0, 1]

D [0, 0, 1]

💡 Hint

Output depends on current state and input at the same clock.

Starting in S0, input 1 gives output 1 and moves to S1. In S1, input 0 gives output 1 and moves to S0. In S0, input 1 gives output 1 and moves to S1. So output sequence is [1,1,1].

🔧 Debug

advanced

Identify the error in FSM output logic

What error will this FSM code cause when synthesized?

Verilog

module fsm_bug(input clk, input rst, input x, output reg z);
  typedef enum logic {IDLE, BUSY} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge rst) begin
    if (rst) state <= IDLE;
    else state <= next_state;
  end

  always_comb begin
    case(state)
      IDLE: begin
        if (x) next_state = BUSY;
        else next_state = IDLE;
      end
      BUSY: begin
        if (!x) next_state = IDLE;
        else next_state = BUSY;
      end
      default: next_state = IDLE;
    endcase
  end

  always_comb begin
    case(state)
      IDLE: z = 0;
      BUSY: z = 1;
      default: z = 0;
    endcase
  end
endmodule

A Output z is not assigned in all cases causing latch

B next_state may be inferred as latch causing synthesis error

C State register is not reset properly causing undefined state

D Syntax error due to missing semicolon

💡 Hint

Check if next_state is assigned in every branch.

In the always_comb block for next_state, some branches do not assign next_state. This causes a latch inference which is usually an error in FSM design.

📝 Syntax

advanced

Syntax error in FSM output logic block

Which option contains the correct syntax for the output logic in a Moore FSM?

Verilog

always_comb begin
  case(state)
    S0: z = 0
    S1: z = 1;
  endcase
end

A always_comb begin\n case(state)\n S0: z = 0;\n S1: z = 1;\n endcase\nend

B always_comb begin\n case state\n S0: z = 0;\n S1: z = 1;\n endcase\nend

C always_comb begin\n case(state)\n S0: z = 0;\n S1: z = 1\n endcase\nend

D

always_comb begin\n  case(state)\n    S0: z = 0;\n    S1: z = 1;\n  endcase\nendcase
end

💡 Hint

Check for missing semicolons and correct case syntax.

Option A has correct syntax with semicolons after each assignment and proper case(state) usage.

🚀 Application

expert

Number of states in a FSM with output logic

A FSM has 3 inputs and 2 outputs. The FSM is Moore type with output depending only on state. How many states are needed to implement all possible output combinations?

A 16

B 8

C 4

D 64

💡 Hint

Think about how many unique output patterns are possible with 2 outputs.

With 2 outputs, there are 2^2 = 4 possible output combinations. To represent all outputs uniquely in a Moore FSM, at least 4 states are needed. But the question asks for all possible output combinations considering inputs and states. Since inputs are 3 bits, total input combinations are 8, but outputs depend only on states. To cover all output combinations, minimum states equal to output combinations (4). However, to implement all input-output mappings, states may be more. The question is about output combinations only, so 4 states suffice. But since the question asks for all possible output combinations, the answer is 4 states. The options include 16 which is 2^(number of outputs + inputs) which is incorrect for Moore FSM output states. The correct answer is 4 states.

Practice

1. Which part of an FSM with output logic determines the output signals based only on the current state?

easy

A. Input decoder

B. Next state logic

C. State register

D. Output logic in a Moore machine

Solution

1. Step 1: Understand FSM output types

   In FSMs, Moore outputs depend only on the current state, while Mealy outputs depend on state and input.

2. Step 2: Identify output logic role

   The output logic in a Moore machine produces outputs based solely on the current state stored in the state register.

3. Final Answer:

   Output logic in a Moore machine -> Option D

4. Quick Check:

   Moore output = state only [OK]

Hint: Moore outputs depend only on state, not inputs [OK]

Common Mistakes:

• Confusing next state logic with output logic
• Thinking outputs depend on inputs in Moore FSM
• Mixing state register role with output logic

2. Which of the following is the correct Verilog syntax to declare a state register named state with 2 bits?

easy

A. reg [1:0] state;

B. wire [2:0] state;

C. reg state[1:0];

D. state reg [1:0];

Solution

1. Step 1: Recall Verilog register declaration

   Registers are declared with reg keyword followed by bit width in brackets, e.g., reg [1:0] for 2 bits.

2. Step 2: Check each option

   reg [1:0] state; correctly declares a 2-bit register named state. wire [2:0] state; uses wire and wrong width. reg state[1:0]; uses incorrect syntax for bit width. state reg [1:0]; has wrong keyword order.

3. Final Answer:

   reg [1:0] state; -> Option A

4. Quick Check:

   reg [1:0] state; is correct syntax [OK]

Hint: Use reg [width-1:0] name; for registers [OK]

Common Mistakes:

• Using wire instead of reg for state registers
• Incorrect bit width syntax like reg name[1:0]
• Wrong keyword order like state reg

3. Given this Verilog snippet for a Moore FSM output logic:

always @(state) begin
  case(state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    2'b10: out = 1'b0;
    default: out = 1'b0;
  endcase
end

What is the output out when state is 2'b01?

medium

A. 1'b0

B. Undefined

C. 1'b1

D. 2'b01

Solution

1. Step 1: Check case for state 2'b01

   The case statement sets out = 1'b1 when state is 2'b01.

2. Step 2: Confirm output value

   Since the state matches 2'b01, output out is assigned 1'b1.

3. Final Answer:

   1'b1 -> Option C

4. Quick Check:

   State 01 -> out = 1 [OK]

Hint: Match state in case to find output quickly [OK]

Common Mistakes:

• Confusing output with state value
• Assuming default applies instead of matching case
• Misreading bit values as decimal

4. Identify the error in this FSM output logic code snippet:

always @(posedge clk) begin
  case(state)
    2'b00: out = 1'b0;
    2'b01: out = 1'b1;
    default: out = 1'b0;
  endcase
end

What is the main problem?

medium

A. Output logic should be in a combinational always block, not clocked

B. Missing reset signal for output

C. State values are incorrectly formatted

D. Output out is not declared as reg

Solution

1. Step 1: Understand output logic timing

   Moore FSM output logic is usually combinational and depends only on state, so it should be in an always block sensitive to state changes, not clock edges.

2. Step 2: Analyze given code

   The code uses always @(posedge clk), making output synchronous, which is incorrect for pure output logic in Moore FSM.

3. Final Answer:

   Output logic should be in a combinational always block, not clocked -> Option A

4. Quick Check:

   Output logic = combinational, not clocked [OK]

Hint: Output logic usually uses always @(*) for combinational [OK]

Common Mistakes:

• Using clocked always block for output logic
• Ignoring sensitivity list correctness
• Confusing output and state update blocks

5. You want to design a Mealy FSM with output logic that sets out = 1 only when the current state is 2'b10 and input in is high. Which Verilog code snippet correctly implements this output logic?

hard

A. always @(in) begin\n if (in)\n out = 1'b1;\n else\n out = 1'b0;\nend

B. always @(state or in) begin\n if (state == 2'b10 && in)\n out = 1'b1;\n else\n out = 1'b0;\nend

C. always @(posedge clk) begin\n if (state == 2'b10 && in)\n out <= 1'b1;\n else\n out <= 1'b0;\nend

D. always @(state) begin\n if (state == 2'b10)\n out = 1'b1;\n else\n out = 1'b0;\nend

Solution

1. Step 1: Understand Mealy output logic

   Mealy outputs depend on both current state and inputs, so sensitivity list must include both state and in.

2. Step 2: Check each option

   always @(state or in) begin\n if (state == 2'b10 && in)\n out = 1'b1;\n else\n out = 1'b0;\nend correctly uses always @(state or in) and sets out based on both conditions. always @(state) begin\n if (state == 2'b10)\n out = 1'b1;\n else\n out = 1'b0;\nend ignores input in. always @(posedge clk) begin\n if (state == 2'b10 && in)\n out <= 1'b1;\n else\n out <= 1'b0;\nend uses clocked block which is not typical for Mealy output logic. always @(in) begin\n if (in)\n out = 1'b1;\n else\n out = 1'b0;\nend ignores state.

3. Final Answer:

   always @(state or in) begin if (state == 2'b10 && in) out = 1'b1; else out = 1'b0; end -> Option B

4. Quick Check:

   Mealy output depends on state and input [OK]

Hint: Include both state and input in sensitivity list for Mealy outputs [OK]

Common Mistakes:

• Leaving input out of sensitivity list
• Using clocked always block for Mealy output
• Ignoring state condition in output logic