FSM with output logic in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a Moore FSM with two states

What is the output z after the FSM processes the input sequence 1, 0, 1?

The FSM has two states: S0 (output 0) and S1 (output 1). It starts in S0. On input 1, it moves from S0 to S1. On input 0, it moves from S1 to S0. Output depends only on the current state.

Verilog

module fsm_moore(input clk, input rst, input x, output reg z);
  typedef enum logic {S0, S1} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else state <= next_state;
  end

  always_comb begin
    case(state)
      S0: next_state = (x) ? S1 : S0;
      S1: next_state = (x) ? S1 : S0;
      default: next_state = S0;
    endcase
  end

  always_comb begin
    case(state)
      S0: z = 0;
      S1: z = 1;
      default: z = 0;
    endcase
  end
endmodule

A [1, 1, 1]

B [0, 0, 1]

C [0, 1, 1]

D [0, 1, 0]

💡 Hint

Remember, output depends only on the current state before input changes.

The FSM starts in S0 (z=0). Input 1: current S0 z=0, next S1. Input 0: current S1 z=1, next S0. Input 1: current S0 z=0, next S1. Output sequence [0,1,0].

❓ Predict Output

intermediate

Output of a Mealy FSM with output on transitions

What is the output z sequence for input 1, 0, 1 on this Mealy FSM?

The FSM has states S0 and S1. It starts in S0. Output z depends on current state and input.

Verilog

module fsm_mealy(input clk, input rst, input x, output reg z);
  typedef enum logic {S0, S1} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge rst) begin
    if (rst) state <= S0;
    else state <= next_state;
  end

  always_comb begin
    case(state)
      S0: begin
        z = x;
        next_state = (x) ? S1 : S0;
      end
      S1: begin
        z = ~x;
        next_state = (x) ? S1 : S0;
      end
      default: begin
        z = 0;
        next_state = S0;
      end
    endcase
  end
endmodule

A [1, 1, 1]

B [0, 1, 0]

C [1, 0, 1]

D [0, 0, 1]

💡 Hint

Output depends on current state and input at the same clock.

Starting in S0, input 1 gives output 1 and moves to S1. In S1, input 0 gives output 1 and moves to S0. In S0, input 1 gives output 1 and moves to S1. So output sequence is [1,1,1].

🔧 Debug

advanced

Identify the error in FSM output logic

What error will this FSM code cause when synthesized?

Verilog

module fsm_bug(input clk, input rst, input x, output reg z);
  typedef enum logic {IDLE, BUSY} state_t;
  state_t state, next_state;

  always_ff @(posedge clk or posedge rst) begin
    if (rst) state <= IDLE;
    else state <= next_state;
  end

  always_comb begin
    case(state)
      IDLE: begin
        if (x) next_state = BUSY;
        else next_state = IDLE;
      end
      BUSY: begin
        if (!x) next_state = IDLE;
        else next_state = BUSY;
      end
      default: next_state = IDLE;
    endcase
  end

  always_comb begin
    case(state)
      IDLE: z = 0;
      BUSY: z = 1;
      default: z = 0;
    endcase
  end
endmodule

A Output z is not assigned in all cases causing latch

B next_state may be inferred as latch causing synthesis error

C State register is not reset properly causing undefined state

D Syntax error due to missing semicolon

💡 Hint

Check if next_state is assigned in every branch.

In the always_comb block for next_state, some branches do not assign next_state. This causes a latch inference which is usually an error in FSM design.

📝 Syntax

advanced

Syntax error in FSM output logic block

Which option contains the correct syntax for the output logic in a Moore FSM?

Verilog

always_comb begin
  case(state)
    S0: z = 0
    S1: z = 1;
  endcase
end

A always_comb begin\n case(state)\n S0: z = 0;\n S1: z = 1;\n endcase\nend

B always_comb begin\n case state\n S0: z = 0;\n S1: z = 1;\n endcase\nend

C always_comb begin\n case(state)\n S0: z = 0;\n S1: z = 1\n endcase\nend

D

always_comb begin\n  case(state)\n    S0: z = 0;\n    S1: z = 1;\n  endcase\nendcase
end

💡 Hint

Check for missing semicolons and correct case syntax.

Option A has correct syntax with semicolons after each assignment and proper case(state) usage.

🚀 Application

expert

Number of states in a FSM with output logic

A FSM has 3 inputs and 2 outputs. The FSM is Moore type with output depending only on state. How many states are needed to implement all possible output combinations?

A 16

B 8

C 4

D 64

💡 Hint

Think about how many unique output patterns are possible with 2 outputs.

With 2 outputs, there are 2^2 = 4 possible output combinations. To represent all outputs uniquely in a Moore FSM, at least 4 states are needed. But the question asks for all possible output combinations considering inputs and states. Since inputs are 3 bits, total input combinations are 8, but outputs depend only on states. To cover all output combinations, minimum states equal to output combinations (4). However, to implement all input-output mappings, states may be more. The question is about output combinations only, so 4 states suffice. But since the question asks for all possible output combinations, the answer is 4 states. The options include 16 which is 2^(number of outputs + inputs) which is incorrect for Moore FSM output states. The correct answer is 4 states.