Sequence detector FSM in Verilog

Introduction

A sequence detector FSM finds a specific pattern of bits in a stream of input bits. It helps digital circuits recognize important signals.

Detecting a special code in a data stream, like a password or command.

Finding a pattern in communication signals to trigger an action.

Checking for errors by spotting known bit sequences.

Controlling devices that respond only when a certain bit pattern appears.

Syntax

Verilog

module sequence_detector(input clk, input reset, input bit_in, output reg detected);
  // State definitions
  typedef enum reg [1:0] {S0, S1, S2, S3} state_t;
  state_t state, next_state;

  // State transition logic
  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  // Next state and output logic
  always @(*) begin
    detected = 0;
    case(state)
      S0: if (bit_in) next_state = S1; else next_state = S0;
      S1: if (bit_in) next_state = S1; else next_state = S2;
      S2: if (bit_in) next_state = S3; else next_state = S0;
      S3: begin
        detected = 1;
        if (bit_in) next_state = S1; else next_state = S2;
      end
      default: next_state = S0;
    endcase
  end
endmodule

This example uses a Moore FSM style where output depends only on the state.

States are defined using an enum for clarity.

Examples

Defines states for the FSM using an enum type.

Verilog

typedef enum reg [1:0] {IDLE, WAIT, MATCH} state_t;
state_t current_state, next_state;

Updates the current state on clock edge or resets it.

Verilog

always @(posedge clk or posedge reset) begin
  if (reset)
    current_state <= IDLE;
  else
    current_state <= next_state;
end

Determines the next state based on current state and input.

Verilog

always @(*) begin
  case(current_state)
    IDLE: if (input_bit) next_state = WAIT; else next_state = IDLE;
    WAIT: if (input_bit) next_state = MATCH; else next_state = IDLE;
    MATCH: next_state = IDLE;
    default: next_state = IDLE;
  endcase
end

Sample Program

This program detects the bit sequence 1011. The testbench sends bits one by one and shows when the sequence is found.

Verilog

module sequence_detector(input clk, input reset, input bit_in, output reg detected);
  typedef enum reg [1:0] {S0, S1, S2, S3} state_t;
  state_t state, next_state;

  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  always @(*) begin
    detected = 0;
    case(state)
      S0: if (bit_in) next_state = S1; else next_state = S0;
      S1: if (bit_in) next_state = S1; else next_state = S2;
      S2: if (bit_in) next_state = S3; else next_state = S0;
      S3: begin
        detected = 1;
        if (bit_in) next_state = S1; else next_state = S2;
      end
      default: next_state = S0;
    endcase
  end
endmodule

// Testbench to simulate the sequence detector
module testbench();
  reg clk = 0;
  reg reset;
  reg bit_in;
  wire detected;

  sequence_detector uut(clk, reset, bit_in, detected);

  always #5 clk = ~clk; // Clock with period 10 units

  initial begin
    reset = 1; bit_in = 0;
    #10 reset = 0;

    // Input bits: 1 0 1 1 0 1
    // The sequence to detect is 1011
    bit_in = 1; #10;
    bit_in = 0; #10;
    bit_in = 1; #10;
    bit_in = 1; #10;
    bit_in = 0; #10;
    bit_in = 1; #10;

    $finish;
  end

  initial begin
    $monitor($time, " ns: bit_in=%b detected=%b", bit_in, detected);
  end
endmodule

Important Notes

The FSM resets to the start state when reset is high.

The detected output goes high only when the full sequence is matched.

Sequence detectors can be designed as Moore or Mealy machines; this example uses Moore.

Summary

A sequence detector FSM watches input bits to find a specific pattern.

It uses states to remember how much of the pattern it has seen.

When the pattern is found, it signals by setting an output high.

Practice

1.

What is the main purpose of a sequence detector FSM in Verilog?

easy

A. To perform arithmetic operations on input data

B. To detect a specific pattern of bits in a serial input stream

C. To generate random numbers

D. To store large amounts of data

Solution

1. Step 1: Understand FSM role

   A sequence detector FSM watches input bits and changes states based on the pattern seen.

2. Step 2: Identify purpose

   Its main job is to find a specific bit pattern in a stream and signal when found.

3. Final Answer:

   To detect a specific pattern of bits in a serial input stream -> Option B

4. Quick Check:

   Sequence detector FSM = pattern detection [OK]

Hint: FSMs track input patterns to signal matches [OK]

Common Mistakes:

• Confusing FSM with memory storage
• Thinking FSM generates data
• Assuming FSM does arithmetic

2.

Which of the following is the correct way to declare a state type for a sequence detector FSM in Verilog?

typedef enum logic [1:0] {S0, S1, S2, S3} state_t;

easy

A. typedef enum logic [1:0] {S0, S1, S2, S3} state_t;

B. enum state_t {S0, S1, S2, S3};

C. typedef enum {S0, S1, S2, S3} state_t;

D. state_t enum logic [1:0] {S0, S1, S2, S3};

Solution

1. Step 1: Check Verilog enum syntax

   SystemVerilog uses 'typedef enum logic [width] {states} name;' to define state types.

2. Step 2: Match correct syntax

   typedef enum logic [1:0] {S0, S1, S2, S3} state_t; matches this syntax exactly, defining 2-bit logic states with typedef.

3. Final Answer:

   typedef enum logic [1:0] {S0, S1, S2, S3} state_t; -> Option A

4. Quick Check:

   Correct enum typedef syntax = typedef enum logic [1:0] {S0, S1, S2, S3} state_t; [OK]

Hint: Use 'typedef enum logic [width]' for states in Verilog [OK]

Common Mistakes:

• Omitting 'typedef' keyword
• Missing logic width specification
• Incorrect order of keywords

3.

Given the following Verilog snippet for a sequence detector FSM that detects "101":

always_ff @(posedge clk or posedge rst) begin
  if (rst) state <= S0;
  else begin
    case(state)
      S0: state <= (in == 1) ? S1 : S0;
      S1: state <= (in == 0) ? S2 : S1;
      S2: state <= (in == 1) ? S3 : S0;
      S3: state <= S0;
    endcase
  end
end

assign detected = (state == S3);

If the input sequence is 1 0 1, what will be the value of detected after the last bit?

medium

A. Undefined

B. 0

C. 1

D. Depends on reset

Solution

1. Step 1: Trace FSM states for input 1,0,1

   Start at S0. Input 1 moves to S1. Input 0 moves to S2. Input 1 moves to S3.

2. Step 2: Check output at S3

   Detected is assigned 1 when state is S3, so after last input detected = 1.

3. Final Answer:

   1 -> Option C

4. Quick Check:

   Sequence 101 detected = 1 [OK]

Hint: Follow states step-by-step for each input bit [OK]

Common Mistakes:

• Not updating state on each clock
• Confusing output with input
• Ignoring reset effect

4.

Identify the error in this Verilog code snippet for a sequence detector FSM:

always_ff @(posedge clk or posedge rst) begin
  if (rst) state <= S0;
  else begin
    case(state)
      S0: if (in == 1) state <= S1;
      S1: if (in == 0) state <= S2;
      S2: if (in == 1) state <= S3;
      S3: state <= S0;
    endcase
  end
end

What is the main problem?

medium

A. Missing default state transition causing latch inference

B. Incorrect sensitivity list in always_ff block

C. Using blocking assignments instead of non-blocking

D. No output signal declared

Solution

1. Step 1: Analyze state transitions

   Each case only assigns state on certain conditions; no else or default to assign state otherwise.

2. Step 2: Understand latch inference

   Missing assignments in some branches cause inferred latches, which is incorrect for FSMs.

3. Final Answer:

   Missing default state transition causing latch inference -> Option A

4. Quick Check:

   All state transitions must be assigned to avoid latches [OK]

Hint: Always assign state in every case branch [OK]

Common Mistakes:

• Not assigning state in else branches
• Using blocking assignments in sequential logic
• Ignoring reset signal

5.

You want to design a sequence detector FSM in Verilog that detects overlapping sequences of "1101" in a serial input stream. Which approach correctly handles overlapping detection?

hard

A. Reset to initial state after full match to allow new detection from next bit

B. Use combinational logic only without states

C. Ignore overlapping sequences and restart detection only after full reset

D. Return to a state representing partial match of last bits to catch overlaps

Solution

1. Step 1: Understand overlapping sequences

   Overlapping means the end of one detected sequence can be the start of another.

2. Step 2: Design FSM to handle overlaps

   FSM must return to a state representing partial match of last bits, not always initial state, to detect overlaps.

3. Final Answer:

   Return to a state representing partial match of last bits to catch overlaps -> Option D

4. Quick Check:

   Partial match states enable overlapping detection [OK]

Hint: Use partial match states to detect overlaps [OK]

Common Mistakes:

• Always resetting to initial state after match
• Ignoring overlap possibility
• Trying to detect sequences without states