Sequence detector FSM in Verilog

Introduction

A sequence detector FSM finds a specific pattern of bits in a stream of input bits. It helps digital circuits recognize important signals.

Detecting a special code in a data stream, like a password or command.

Finding a pattern in communication signals to trigger an action.

Checking for errors by spotting known bit sequences.

Controlling devices that respond only when a certain bit pattern appears.

Syntax

Verilog

module sequence_detector(input clk, input reset, input bit_in, output reg detected);
  // State definitions
  typedef enum reg [1:0] {S0, S1, S2, S3} state_t;
  state_t state, next_state;

  // State transition logic
  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  // Next state and output logic
  always @(*) begin
    detected = 0;
    case(state)
      S0: if (bit_in) next_state = S1; else next_state = S0;
      S1: if (bit_in) next_state = S1; else next_state = S2;
      S2: if (bit_in) next_state = S3; else next_state = S0;
      S3: begin
        detected = 1;
        if (bit_in) next_state = S1; else next_state = S2;
      end
      default: next_state = S0;
    endcase
  end
endmodule

This example uses a Moore FSM style where output depends only on the state.

States are defined using an enum for clarity.

Examples

Defines states for the FSM using an enum type.

Verilog

typedef enum reg [1:0] {IDLE, WAIT, MATCH} state_t;
state_t current_state, next_state;

Updates the current state on clock edge or resets it.

Verilog

always @(posedge clk or posedge reset) begin
  if (reset)
    current_state <= IDLE;
  else
    current_state <= next_state;
end

Determines the next state based on current state and input.

Verilog

always @(*) begin
  case(current_state)
    IDLE: if (input_bit) next_state = WAIT; else next_state = IDLE;
    WAIT: if (input_bit) next_state = MATCH; else next_state = IDLE;
    MATCH: next_state = IDLE;
    default: next_state = IDLE;
  endcase
end

Sample Program

This program detects the bit sequence 1011. The testbench sends bits one by one and shows when the sequence is found.

Verilog

module sequence_detector(input clk, input reset, input bit_in, output reg detected);
  typedef enum reg [1:0] {S0, S1, S2, S3} state_t;
  state_t state, next_state;

  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  always @(*) begin
    detected = 0;
    case(state)
      S0: if (bit_in) next_state = S1; else next_state = S0;
      S1: if (bit_in) next_state = S1; else next_state = S2;
      S2: if (bit_in) next_state = S3; else next_state = S0;
      S3: begin
        detected = 1;
        if (bit_in) next_state = S1; else next_state = S2;
      end
      default: next_state = S0;
    endcase
  end
endmodule

// Testbench to simulate the sequence detector
module testbench();
  reg clk = 0;
  reg reset;
  reg bit_in;
  wire detected;

  sequence_detector uut(clk, reset, bit_in, detected);

  always #5 clk = ~clk; // Clock with period 10 units

  initial begin
    reset = 1; bit_in = 0;
    #10 reset = 0;

    // Input bits: 1 0 1 1 0 1
    // The sequence to detect is 1011
    bit_in = 1; #10;
    bit_in = 0; #10;
    bit_in = 1; #10;
    bit_in = 1; #10;
    bit_in = 0; #10;
    bit_in = 1; #10;

    $finish;
  end

  initial begin
    $monitor($time, " ns: bit_in=%b detected=%b", bit_in, detected);
  end
endmodule

Important Notes

The FSM resets to the start state when reset is high.

The detected output goes high only when the full sequence is matched.

Sequence detectors can be designed as Moore or Mealy machines; this example uses Moore.

Summary

A sequence detector FSM watches input bits to find a specific pattern.

It uses states to remember how much of the pattern it has seen.

When the pattern is found, it signals by setting an output high.