D flip-flop with asynchronous reset in Verilog

Introduction

A D flip-flop stores a single bit of data on a clock edge. An asynchronous reset lets you clear the stored data immediately, without waiting for the clock.

You want to save a bit of information synchronized to a clock signal.

You need to clear the stored data instantly when a reset signal is activated.

You are designing a memory element in digital circuits.

You want to control data flow in a sequential logic circuit.

You want to build counters or registers that can be reset anytime.

Syntax

Verilog

module d_flip_flop_async_reset(
    input wire clk,
    input wire reset_n,  // active low asynchronous reset
    input wire d,
    output reg q
);

always @(posedge clk or negedge reset_n) begin
    if (!reset_n)
        q <= 1'b0;
    else
        q <= d;
end

endmodule

The reset signal is asynchronous, so it works immediately when active, ignoring the clock.

The reset is active low in this example, meaning it resets when reset_n is 0.

Examples

This example uses an active high asynchronous reset, which resets when reset is 1.

Verilog

always @(posedge clk or posedge reset) begin
    if (reset)
        q <= 1'b0;
    else
        q <= d;
end

This example shows a synchronous reset, which only resets on the clock edge.

Verilog

always @(posedge clk) begin
    if (reset)  // synchronous reset
        q <= 1'b0;
    else
        q <= d;
end

Sample Program

This testbench shows the D flip-flop with asynchronous reset. The reset clears the output immediately when active, regardless of the clock.

Verilog

module testbench;
    reg clk = 0;
    reg reset_n = 1;
    reg d = 0;
    wire q;

    d_flip_flop_async_reset uut (
        .clk(clk),
        .reset_n(reset_n),
        .d(d),
        .q(q)
    );

    // Clock generation
    always #5 clk = ~clk;

    initial begin
        $monitor($time, " clk=%b reset_n=%b d=%b q=%b", clk, reset_n, d, q);

        // Start with reset active
        reset_n = 0;
        d = 0;
        #10;

        reset_n = 1; // release reset
        d = 1;
        #10;

        d = 0;
        #10;

        reset_n = 0; // assert reset asynchronously
        #7;

        reset_n = 1; // release reset
        d = 1;
        #10;

        $finish;
    end
endmodule

Important Notes

Asynchronous reset works immediately, so output changes as soon as reset activates.

Make sure to use non-blocking assignments (<=) inside always blocks for sequential logic.

Active low reset signals are common in hardware design but can be active high depending on your circuit.

Summary

A D flip-flop stores data on the clock's rising edge.

An asynchronous reset clears the output immediately, ignoring the clock.

Use asynchronous reset to quickly clear registers or memory elements.

Practice

1.

What does the asynchronous reset in a D flip-flop do?

easy

A. It stores the input data only on the falling edge of the clock.

B. It clears the output immediately, ignoring the clock signal.

C. It delays the output change until the next clock cycle.

D. It toggles the output on every clock pulse.

Solution

1. Step 1: Understand asynchronous reset behavior

   Asynchronous reset forces the output to zero immediately, without waiting for the clock edge.

2. Step 2: Compare with other options

   Other options describe clock-dependent or toggling behavior, which is not asynchronous reset.

3. Final Answer:

   It clears the output immediately, ignoring the clock signal. -> Option B

4. Quick Check:

   Asynchronous reset = immediate clear [OK]

Hint: Async reset clears output instantly, no clock needed [OK]

Common Mistakes:

• Confusing asynchronous reset with synchronous reset
• Thinking reset waits for clock edge
• Mixing reset with toggle or clock enable

2.

Which of the following is the correct Verilog sensitivity list for a D flip-flop with asynchronous reset?

module dff(input clk, input rst_n, input d, output reg q);

easy

A. always @(rst_n or clk)

B. always @(posedge clk and negedge rst_n)

C. always @(posedge clk or negedge rst_n)

D. always @(posedge clk)

Solution

1. Step 1: Identify asynchronous reset sensitivity

   Asynchronous reset triggers on reset signal edge, so sensitivity list must include clock posedge and reset negedge.

2. Step 2: Check syntax correctness

   always @(posedge clk or negedge rst_n) uses 'or' to combine posedge clk and negedge rst_n, which is correct syntax.

3. Final Answer:

   always @(posedge clk or negedge rst_n) -> Option C

4. Quick Check:

   Sensitivity list uses 'or' for async reset [OK]

Hint: Use 'or' in sensitivity list for async reset [OK]

Common Mistakes:

• Using 'and' instead of 'or' in sensitivity list
• Omitting reset from sensitivity list
• Using only clock edge without reset

3.

Given the following Verilog code, what is the value of q after the reset is deasserted and one clock rising edge occurs with d = 1?

module dff(input clk, input rst_n, input d, output reg q);
  always @(posedge clk or negedge rst_n) begin
    if (!rst_n)
      q <= 0;
    else
      q <= d;
  end
endmodule

medium

A. q = 1

B. q retains previous value

C. q = 0

D. q is undefined

Solution

1. Step 1: Analyze reset effect

   When rst_n is low, q is set to 0 immediately.

2. Step 2: Analyze clock edge after reset

   After reset is released (rst_n=1), on next posedge clk, q takes value of d, which is 1.

3. Final Answer:

   q = 1 -> Option A

4. Quick Check:

   After reset, q follows d on clock edge [OK]

Hint: After reset, q updates to d on clock rising edge [OK]

Common Mistakes:

• Assuming q stays 0 after reset
• Ignoring clock edge for q update
• Thinking q is undefined after reset

4.

Identify the error in this D flip-flop with asynchronous reset code snippet:

always @(posedge clk or posedge rst_n) begin
  if (!rst_n)
    q <= 0;
  else
    q <= d;
end

medium

A. Reset edge should be negedge, not posedge.

B. Missing sensitivity to clock negedge.

C. The reset condition should check rst_n, not !rst_n.

D. The output q should not be declared as reg.

Solution

1. Step 1: Check reset polarity

   The reset is active low, so sensitivity should be on negedge rst_n, not posedge.

2. Step 2: Verify reset condition

   The condition uses !rst_n correctly for active low reset.

3. Final Answer:

   Reset edge should be negedge, not posedge. -> Option A

4. Quick Check:

   Active low reset uses negedge in sensitivity [OK]

Hint: Active low reset uses negedge, not posedge [OK]

Common Mistakes:

• Using posedge for active low reset
• Confusing reset polarity and condition
• Adding unnecessary clock edges

5.

You want to design a D flip-flop with asynchronous reset that sets q to 1 when reset is active (active low). Which code snippet correctly implements this behavior?

always @(posedge clk or negedge rst_n) begin
  if (!rst_n)
    q <= 1;
  else
    q <= d;
end

hard

A. The reset condition should be if (rst_n) instead of if (!rst_n).

B. Reset should set q to 0, not 1, so this code is incorrect.

C. Sensitivity list should use posedge rst_n for active low reset.

D. This code correctly sets q to 1 on reset and updates q on clock.

Solution

1. Step 1: Check reset polarity and action

   Reset is active low (negedge rst_n), and when active (!rst_n), q is set to 1 as required.

2. Step 2: Verify normal operation

   When reset is not active, q follows d on clock rising edge.

3. Final Answer:

   This code correctly sets q to 1 on reset and updates q on clock. -> Option D

4. Quick Check:

   Active low reset sets q=1, else q=d [OK]

Hint: Active low reset uses negedge and !rst_n condition [OK]

Common Mistakes:

• Assuming reset must clear q to 0
• Using posedge for active low reset
• Reversing reset condition logic