D flip-flop with asynchronous reset in Verilog

Introduction

A D flip-flop stores a single bit of data on a clock edge. An asynchronous reset lets you clear the stored data immediately, without waiting for the clock.

You want to save a bit of information synchronized to a clock signal.

You need to clear the stored data instantly when a reset signal is activated.

You are designing a memory element in digital circuits.

You want to control data flow in a sequential logic circuit.

You want to build counters or registers that can be reset anytime.

Syntax

Verilog

module d_flip_flop_async_reset(
    input wire clk,
    input wire reset_n,  // active low asynchronous reset
    input wire d,
    output reg q
);

always @(posedge clk or negedge reset_n) begin
    if (!reset_n)
        q <= 1'b0;
    else
        q <= d;
end

endmodule

The reset signal is asynchronous, so it works immediately when active, ignoring the clock.

The reset is active low in this example, meaning it resets when reset_n is 0.

Examples

This example uses an active high asynchronous reset, which resets when reset is 1.

Verilog

always @(posedge clk or posedge reset) begin
    if (reset)
        q <= 1'b0;
    else
        q <= d;
end

This example shows a synchronous reset, which only resets on the clock edge.

Verilog

always @(posedge clk) begin
    if (reset)  // synchronous reset
        q <= 1'b0;
    else
        q <= d;
end

Sample Program

This testbench shows the D flip-flop with asynchronous reset. The reset clears the output immediately when active, regardless of the clock.

Verilog

module testbench;
    reg clk = 0;
    reg reset_n = 1;
    reg d = 0;
    wire q;

    d_flip_flop_async_reset uut (
        .clk(clk),
        .reset_n(reset_n),
        .d(d),
        .q(q)
    );

    // Clock generation
    always #5 clk = ~clk;

    initial begin
        $monitor($time, " clk=%b reset_n=%b d=%b q=%b", clk, reset_n, d, q);

        // Start with reset active
        reset_n = 0;
        d = 0;
        #10;

        reset_n = 1; // release reset
        d = 1;
        #10;

        d = 0;
        #10;

        reset_n = 0; // assert reset asynchronously
        #7;

        reset_n = 1; // release reset
        d = 1;
        #10;

        $finish;
    end
endmodule

Important Notes

Asynchronous reset works immediately, so output changes as soon as reset activates.

Make sure to use non-blocking assignments (<=) inside always blocks for sequential logic.

Active low reset signals are common in hardware design but can be active high depending on your circuit.

Summary

A D flip-flop stores data on the clock's rising edge.

An asynchronous reset clears the output immediately, ignoring the clock.

Use asynchronous reset to quickly clear registers or memory elements.