D flip-flop with clock edge in Verilog

Introduction

A D flip-flop stores a single bit of data and changes its output only at the clock's edge. This helps keep data stable and synchronized in digital circuits.

To store a bit of information that updates only when a clock signal changes.

When building memory elements like registers in a digital system.

To synchronize signals between different parts of a circuit.

When you want to avoid glitches by updating data only on clock edges.

Syntax

Verilog

module d_flip_flop(
    input wire clk,
    input wire d,
    output reg q
);

always @(posedge clk) begin
    q <= d;
end

endmodule

posedge clk means the code runs when the clock signal changes from 0 to 1 (rising edge).

The q <= d; line updates the output q with the input d at the clock edge.

Examples

Updates output q on the rising edge of the clock.

Verilog

always @(posedge clk) begin
    q <= d;
end

Updates output q on the falling edge of the clock (when clock goes from 1 to 0).

Verilog

always @(negedge clk) begin
    q <= d;
end

A D flip-flop with asynchronous reset that clears output q when rst is high.

Verilog

module dff_async_reset(
    input wire clk,
    input wire rst,
    input wire d,
    output reg q
);

always @(posedge clk or posedge rst) begin
    if (rst)
        q <= 0;
    else
        q <= d;
end

endmodule

Sample Program

This testbench creates a clock signal and changes the input d. The output q updates only on the rising edge of the clock, showing how the D flip-flop stores data.

Verilog

module testbench;
    reg clk = 0;
    reg d = 0;
    wire q;

    d_flip_flop uut (
        .clk(clk),
        .d(d),
        .q(q)
    );

    always #5 clk = ~clk; // Clock toggles every 5 time units

    initial begin
        $monitor($time, ": clk=%b d=%b q=%b", clk, d, q);

        d = 0; #10;
        d = 1; #10;
        d = 0; #10;
        d = 1; #10;
        $finish;
    end
endmodule

module d_flip_flop(
    input wire clk,
    input wire d,
    output reg q
);

always @(posedge clk) begin
    q <= d;
end

endmodule

Important Notes

The output q changes only at the clock's rising edge, not immediately when d changes.

Using non-blocking assignment <= inside always block is important for correct timing behavior.

Initial value of q is unknown (shown as 'x') until the first clock edge.

Summary

A D flip-flop stores data on the clock's rising edge.

Use always @(posedge clk) to trigger updates.

It helps keep digital circuits synchronized and stable.

Practice

1.

What does a D flip-flop do in a digital circuit?

easy

A. Stores the input value on the rising edge of the clock

B. Generates a clock signal

C. Performs arithmetic operations

D. Resets the circuit asynchronously

Solution

1. Step 1: Understand the role of a D flip-flop

   A D flip-flop captures and stores the input value (D) at a specific clock event.

2. Step 2: Identify the clock event

   It stores the value on the rising edge (positive edge) of the clock signal.

3. Final Answer:

   Stores the input value on the rising edge of the clock -> Option A

4. Quick Check:

   D flip-flop stores input on clock rising edge [OK]

Hint: Remember: D flip-flop stores data at clock's rising edge [OK]

Common Mistakes:

• Confusing D flip-flop with clock generator
• Thinking it performs calculations
• Assuming it resets asynchronously

2.

Which of the following is the correct Verilog syntax to trigger a D flip-flop on the rising edge of the clock clk?

easy

A. always @(negedge clk)

B. always @(posedge clk)

C. always @(clk)

D. always @(clk posedge)

Solution

1. Step 1: Recall the correct event control syntax

   Verilog uses posedge to detect the rising edge of a signal.

2. Step 2: Match syntax with clock signal

   The correct syntax to trigger on rising edge of clk is always @(posedge clk).

3. Final Answer:

   always @(posedge clk) -> Option B

4. Quick Check:

   Rising edge trigger = posedge [OK]

Hint: Use 'posedge' for rising edge in always block [OK]

Common Mistakes:

• Using negedge instead of posedge
• Omitting posedge keyword
• Incorrect event control syntax

3.

What will be the output q after the following Verilog code runs for one clock cycle if d = 1 and initial q = 0?

module dff(input clk, input d, output reg q);
  always @(posedge clk) begin
    q <= d;
  end
endmodule

medium

A. q remains 0

B. q toggles between 0 and 1

C. q becomes undefined

D. q becomes 1

Solution

1. Step 1: Understand the behavior on posedge clk

   On the rising edge of clk, the flip-flop assigns d to q.

2. Step 2: Apply given inputs

   Since d = 1 and initial q = 0, after the clock edge, q updates to 1.

3. Final Answer:

   q becomes 1 -> Option D

4. Quick Check:

   D input 1 stored at clock edge = q 1 [OK]

Hint: On clock rising edge, q copies d value [OK]

Common Mistakes:

• Assuming q changes immediately without clock edge
• Thinking q toggles automatically
• Ignoring initial value of q

4.

Identify the error in this D flip-flop Verilog code snippet:

module dff(input clk, input d, output reg q);
  always @(clk) begin
    q <= d;
  end
endmodule

medium

A. Missing sensitivity to clock edge, should use posedge

B. Output q should not be reg

C. Input d should be reg type

D. No error, code is correct

Solution

1. Step 1: Check sensitivity list

   The code uses always @(clk), which triggers on any change of clk, not just edges.

2. Step 2: Correct edge sensitivity

   For a D flip-flop, it must trigger only on the rising edge: always @(posedge clk).

3. Final Answer:

   Missing sensitivity to clock edge, should use posedge -> Option A

4. Quick Check:

   Flip-flop triggers on posedge clk only [OK]

Hint: Use posedge in always block for flip-flop [OK]

Common Mistakes:

• Using level sensitivity instead of edge sensitivity
• Confusing reg and wire for outputs
• Assuming inputs must be reg

5.

You want to design a D flip-flop that resets q to 0 asynchronously when rst is high. Which Verilog code snippet correctly implements this behavior?

module dff(input clk, input rst, input d, output reg q);
  always @(posedge clk or posedge rst) begin
    if (rst)
      q <= 0;
    else
      q <= d;
  end
endmodule

hard

A. The sensitivity list is missing negedge rst

B. Reset should be checked only on clock edge, not asynchronously

C. This code correctly implements asynchronous reset

D. q should be assigned with blocking assignment (=) inside always

Solution

1. Step 1: Analyze sensitivity list

   The always block triggers on rising edge of clock or rising edge of reset, enabling asynchronous reset.

2. Step 2: Check reset logic

   If reset is high, q is set to 0 immediately, else q follows d on clock edge.

3. Final Answer:

   This code correctly implements asynchronous reset -> Option C

4. Quick Check:

   Asynchronous reset uses posedge rst in sensitivity list [OK]

Hint: Add posedge rst in sensitivity list for async reset [OK]

Common Mistakes:

• Checking reset only on clock edge (synchronous reset)
• Using blocking assignment for sequential logic
• Missing reset in sensitivity list