JK flip-flop behavior in Verilog

Introduction

A JK flip-flop is a basic memory element in digital circuits. It helps store and change a bit of information based on inputs.

To store a single bit of data in a digital system.

To build counters that count up or down.

To create memory elements in sequential logic circuits.

To toggle outputs when both inputs are high.

To control state changes in simple digital devices.

Syntax

Verilog

always @(posedge clk or negedge reset) begin
  if (!reset)
    q <= 0;
  else begin
    case ({j, k})
      2'b00: q <= q;       // No change
      2'b01: q <= 0;       // Reset
      2'b10: q <= 1;       // Set
      2'b11: q <= ~q;      // Toggle
    endcase
  end
end

The flip-flop changes output only on the clock's rising edge or when reset is active.

Inputs J and K control how the output Q changes.

Examples

This example shows the JK flip-flop behavior using if-else statements.

Verilog

always @(posedge clk) begin
  if (reset == 0)
    q <= 0;
  else if (j == 0 && k == 0)
    q <= q; // Hold
  else if (j == 0 && k == 1)
    q <= 0; // Reset
  else if (j == 1 && k == 0)
    q <= 1; // Set
  else
    q <= ~q; // Toggle
end

This example uses a case statement and resets on the positive edge of reset.

Verilog

always @(posedge clk or posedge reset) begin
  if (reset)
    q <= 0;
  else
    case ({j, k})
      2'b00: q <= q;
      2'b01: q <= 0;
      2'b10: q <= 1;
      2'b11: q <= ~q;
    endcase
end

Sample Program

This program defines a JK flip-flop module and a testbench that shows how the output Q changes with different J and K inputs on clock edges.

Verilog

module jk_flip_flop(
  input wire clk,
  input wire reset,
  input wire j,
  input wire k,
  output reg q
);

  always @(posedge clk or negedge reset) begin
    if (!reset)
      q <= 0;
    else begin
      case ({j, k})
        2'b00: q <= q;       // No change
        2'b01: q <= 0;       // Reset
        2'b10: q <= 1;       // Set
        2'b11: q <= ~q;      // Toggle
      endcase
    end
  end
endmodule

// Testbench
module testbench;
  reg clk = 0;
  reg reset;
  reg j;
  reg k;
  wire q;

  jk_flip_flop uut(.clk(clk), .reset(reset), .j(j), .k(k), .q(q));

  always #5 clk = ~clk; // Clock toggles every 5 time units

  initial begin
    $monitor($time, ": reset=%b j=%b k=%b q=%b", reset, j, k, q);

    reset = 0; j = 0; k = 0;
    #10 reset = 1; // Release reset

    #10 j = 0; k = 0; // Hold
    #10 j = 1; k = 0; // Set
    #10 j = 0; k = 1; // Reset
    #10 j = 1; k = 1; // Toggle
    #10 j = 1; k = 1; // Toggle again
    #10 j = 0; k = 0; // Hold
    #10 $finish;
  end
endmodule

Important Notes

Reset is usually asynchronous to quickly clear the flip-flop.

When both J and K are 1, the flip-flop toggles its output.

Make sure clock and reset signals are clean to avoid unexpected behavior.

Summary

JK flip-flop stores one bit and changes output based on J and K inputs.

It can hold, set, reset, or toggle the output.

Used widely in digital circuits for memory and counting.