D flip-flop with synchronous reset in Verilog

Introduction

A D flip-flop stores a bit of data on a clock edge. The synchronous reset lets you clear the stored data at the same time as the clock, making control easier.

When you want to save a bit of information that changes only on clock signals.

When you need to reset the stored data exactly on a clock edge, not anytime.

When designing digital circuits like counters or registers that need controlled reset.

When you want predictable timing for clearing data in your circuit.

Syntax

Verilog

module d_flip_flop_sync_reset(
    input wire clk,
    input wire reset,
    input wire d,
    output reg q
);

always @(posedge clk) begin
    if (reset) begin
        q <= 1'b0;
    end else begin
        q <= d;
    end
end

endmodule

The reset is checked inside the clock edge block, so it happens only on the clock's rising edge.

The output q is declared as reg because it holds state.

Examples

Simple synchronous reset inside the clock edge block.

Verilog

always @(posedge clk) begin
    if (reset) q <= 1'b0;
    else q <= d;
end

Full module example with synchronous reset.

Verilog

module dff_sync_reset(
    input clk, reset, d,
    output reg q
);

always @(posedge clk) begin
    if (reset) q <= 1'b0;
    else q <= d;
end

endmodule

Sample Program

This testbench toggles the clock every 5 time units. It applies reset and data inputs to the D flip-flop with synchronous reset. The monitor prints the signals at every change.

Verilog

module testbench;
    reg clk = 0;
    reg reset;
    reg d;
    wire q;

    d_flip_flop_sync_reset uut(
        .clk(clk),
        .reset(reset),
        .d(d),
        .q(q)
    );

    always #5 clk = ~clk; // Clock toggles every 5 time units

    initial begin
        reset = 1;
        d = 0;
        #10;
        reset = 0;
        d = 1;
        #10;
        d = 0;
        #10;
        reset = 1;
        #10;
        reset = 0;
        d = 1;
        #10;
        $finish;
    end

    initial begin
        $monitor($time, " clk=%b reset=%b d=%b q=%b", clk, reset, d, q);
    end
endmodule

Important Notes

Synchronous reset means reset only works on the clock edge, unlike asynchronous reset which works anytime.

Make sure the reset signal is stable before the clock edge to avoid unexpected behavior.

Summary

D flip-flop stores data on clock edges.

Synchronous reset clears data only on clock edges.

This helps control timing and predict circuit behavior.