When to use non-blocking (sequential) in Verilog

Introduction

Non-blocking assignments let you update many signals at the same time in a sequence. This helps model real hardware where changes happen together, not one after another.

When you want to describe how flip-flops update their outputs on a clock edge.

When you need to write sequential logic that updates multiple registers simultaneously.

When you want to avoid unintended order effects in your code that can cause bugs.

When modeling synchronous circuits where all changes happen in parallel at clock ticks.

When you want to write clear code that matches how hardware actually works.

Syntax

Verilog

always @(posedge clk) begin
  signal1 <= value1;
  signal2 <= value2;
end

Use the '<=' symbol for non-blocking assignments inside sequential blocks.

All non-blocking assignments in the same block update their targets simultaneously after the block finishes.

Examples

Both 'a' and 'b' update at the same time using the old values of 'b' and 'c'.

Verilog

always @(posedge clk) begin
  a <= b;
  b <= c;
end

Increment a counter on each clock tick using non-blocking assignment.

Verilog

always @(posedge clk) begin
  count <= count + 1;
end

Sample Program

This module counts up by one on each clock pulse. When reset is high, it sets count to zero. Non-blocking assignments ensure the count updates correctly on each clock edge.

Verilog

module simple_counter(
  input wire clk,
  input wire reset,
  output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
  if (reset) begin
    count <= 4'b0000;
  end else begin
    count <= count + 1;
  end
end

endmodule

Important Notes

Do not mix blocking (=) and non-blocking (<=) assignments in the same sequential block to avoid confusion.

Non-blocking assignments help prevent race conditions in sequential logic.

Summary

Use non-blocking assignments to model hardware registers updating together on clock edges.

They keep your sequential logic clear and bug-free by updating all signals simultaneously.