When to use non-blocking (sequential) in Verilog

Introduction

Non-blocking assignments let you update many signals at the same time in a sequence. This helps model real hardware where changes happen together, not one after another.

When you want to describe how flip-flops update their outputs on a clock edge.

When you need to write sequential logic that updates multiple registers simultaneously.

When you want to avoid unintended order effects in your code that can cause bugs.

When modeling synchronous circuits where all changes happen in parallel at clock ticks.

When you want to write clear code that matches how hardware actually works.

Syntax

Verilog

always @(posedge clk) begin
  signal1 <= value1;
  signal2 <= value2;
end

Use the '<=' symbol for non-blocking assignments inside sequential blocks.

All non-blocking assignments in the same block update their targets simultaneously after the block finishes.

Examples

Both 'a' and 'b' update at the same time using the old values of 'b' and 'c'.

Verilog

always @(posedge clk) begin
  a <= b;
  b <= c;
end

Increment a counter on each clock tick using non-blocking assignment.

Verilog

always @(posedge clk) begin
  count <= count + 1;
end

Sample Program

This module counts up by one on each clock pulse. When reset is high, it sets count to zero. Non-blocking assignments ensure the count updates correctly on each clock edge.

Verilog

module simple_counter(
  input wire clk,
  input wire reset,
  output reg [3:0] count
);

always @(posedge clk or posedge reset) begin
  if (reset) begin
    count <= 4'b0000;
  end else begin
    count <= count + 1;
  end
end

endmodule

Important Notes

Do not mix blocking (=) and non-blocking (<=) assignments in the same sequential block to avoid confusion.

Non-blocking assignments help prevent race conditions in sequential logic.

Summary

Use non-blocking assignments to model hardware registers updating together on clock edges.

They keep your sequential logic clear and bug-free by updating all signals simultaneously.

Practice

1. When should you use non-blocking assignments (<=) in Verilog?

easy

A. To declare constants in your design

B. To model sequential logic that updates on clock edges

C. To model combinational logic with immediate updates

D. To assign values outside of always blocks

Solution

1. Step 1: Understand the purpose of non-blocking assignments

   Non-blocking assignments (<=) are used to model sequential logic, which updates values on clock edges, like flip-flops.

2. Step 2: Differentiate from other assignment types

   Blocking assignments (=) are used for combinational logic with immediate updates, not sequential logic.

3. Final Answer:

   To model sequential logic that updates on clock edges -> Option B

4. Quick Check:

   Non-blocking = sequential logic [OK]

Hint: Use non-blocking for clocked (sequential) logic only [OK]

Common Mistakes:

• Using non-blocking for combinational logic
• Confusing blocking and non-blocking assignments
• Assigning outside always blocks

2. Which of the following is the correct syntax for a non-blocking assignment inside an always block triggered on a clock edge?

easy

A. always @(posedge clk) begin a <= b; end

B. always @(posedge clk) begin a = b; end

C. always @(clk) begin a <= b; end

D. always @(posedge clk) a = b;

Solution

1. Step 1: Identify the correct event control

   The always block should trigger on the positive edge of the clock: posedge clk.

2. Step 2: Use non-blocking assignment inside the block

   Non-blocking assignment uses <= to update signals sequentially.

3. Final Answer:

   always @(posedge clk) begin a <= b; end -> Option A

4. Quick Check:

   Non-blocking inside posedge always block = correct syntax [OK]

Hint: Use '<= ' inside 'always @(posedge clk)' for sequential logic [OK]

Common Mistakes:

• Using blocking '=' instead of '<=' in sequential blocks
• Triggering always block on wrong event
• Missing begin-end for multiple statements

3. What is the output of this Verilog code snippet after one positive clock edge?

reg a, b;
always @(posedge clk) begin
  a <= b;
  b <= 1'b1;
end

Assuming initial values a=0 and b=0.

medium

A. a=0, b=1

B. a=1, b=1

C. a=0, b=0

D. a=1, b=0

Solution

1. Step 1: Understand non-blocking update behavior

   Non-blocking assignments update all variables simultaneously after the always block finishes.

2. Step 2: Trace values before and after clock edge

   Before clock edge: a=0, b=0.
   At clock edge: a gets old b (0), b gets 1.
   After update: a=0, b=1.

3. Final Answer:

   a=0, b=1 -> Option A

4. Quick Check:

   Non-blocking updates use old values simultaneously [OK]

Hint: Non-blocking uses old values simultaneously on clock edge [OK]

Common Mistakes:

• Thinking 'a' updates immediately with new 'b'
• Confusing blocking and non-blocking timing
• Ignoring initial values

4. Identify the error in this Verilog code snippet:

always @(posedge clk) begin
  a = b;
  b = 1'b1;
end

where a and b are registers updated on clock edge.

medium

A. Missing sensitivity list for combinational logic

B. Using non-blocking assignments outside always block

C. Incorrect data types for registers

D. Using blocking assignments instead of non-blocking in sequential logic

Solution

1. Step 1: Check assignment type in clocked always block

   Sequential logic triggered on clock edges should use non-blocking assignments (<=), not blocking (=).

2. Step 2: Understand consequences of blocking in sequential logic

   Blocking assignments cause race conditions and incorrect simulation of flip-flops.

3. Final Answer:

   Using blocking assignments instead of non-blocking in sequential logic -> Option D

4. Quick Check:

   Sequential logic needs non-blocking assignments [OK]

Hint: Use '<=' in clocked always blocks to avoid race conditions [OK]

Common Mistakes:

• Using '=' in clocked always blocks
• Ignoring race condition risks
• Confusing sensitivity lists

5. You want to design a 2-bit register that updates both bits simultaneously on the rising edge of clk. Which code snippet correctly uses non-blocking assignments to avoid race conditions?

A) always @(posedge clk) begin
  bit0 <= bit1;
  bit1 <= bit0;
end

B) always @(posedge clk) begin
  bit0 = bit1;
  bit1 = bit0;
end

C) always @(posedge clk) begin
  bit0 <= bit1;
  bit1 <= bit1;
end

D) always @(posedge clk) begin
  bit0 = bit0;
  bit1 = bit1;
end

hard

A. Assigns bit1 to both bits, losing original bit0

B. Uses blocking assignments causing race conditions

C. Swaps bits correctly using non-blocking assignments

D. No change in bits, blocking assignments used

Solution

1. Step 1: Analyze non-blocking assignments in Swaps bits correctly using non-blocking assignments

   Swaps bits correctly using non-blocking assignments uses non-blocking assignments to swap bit0 and bit1 simultaneously, avoiding race conditions.

2. Step 2: Compare with other options

   Uses blocking assignments causing race conditions uses blocking assignments causing race conditions.
   Assigns bit1 to both bits, losing original bit0 overwrites bit0 and bit1 incorrectly.
   No change in bits, blocking assignments used does not change bits and uses blocking assignments.

3. Final Answer:

   Swaps bits correctly using non-blocking assignments -> Option C

4. Quick Check:

   Non-blocking swaps bits simultaneously [OK]

Hint: Use non-blocking to swap registers simultaneously on clock edge [OK]

Common Mistakes:

• Using blocking assignments in sequential logic
• Overwriting values before reading them
• Not updating both bits simultaneously