FSM with output logic in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What is an FSM with output logic in Verilog?

An FSM (Finite State Machine) with output logic is a design where outputs depend on the current state and possibly inputs. It controls outputs based on the state transitions defined in the FSM.

beginner

What are the two main types of FSM output logic?

The two main types are Mealy and Moore machines. Mealy outputs depend on state and inputs, while Moore outputs depend only on the current state.

intermediate

In Verilog, where is the output logic usually coded in an FSM?

Output logic is usually coded in a separate always block or inside the state machine block, depending on whether it is Mealy or Moore type, to clearly separate state transitions and output assignments.

intermediate

What is the difference between Mealy and Moore FSM output timing?

Mealy outputs can change immediately with inputs, causing outputs to change within a clock cycle. Moore outputs change only on state changes, synchronized with the clock.

intermediate

Why is it important to separate state transition logic and output logic in FSM design?

Separating them improves readability, makes debugging easier, and helps avoid unintended glitches in outputs by clearly defining when outputs change.

In a Moore FSM, outputs depend on:

A Only inputs

B Current state and inputs

C Previous state

D Only the current state

Moore FSM outputs depend only on the current state, not directly on inputs.

Which type of FSM output can change asynchronously with inputs?

A Mealy

B Neither

C Both Moore and Mealy

D Moore

Mealy FSM outputs depend on inputs and can change immediately when inputs change.

In Verilog FSM design, what keyword is commonly used to define state transitions?

A always_ff

B case

C always_comb

D if

The 'case' statement is commonly used to define state transitions based on the current state.

What is a common way to represent states in Verilog FSMs?

A Using enumerated types or parameters

B Using integers directly

C Using strings

D Using floating point numbers

States are usually represented using parameters or enumerated types for clarity and maintainability.

Why might you separate output logic from state transition logic in FSM code?

A To make outputs faster

B To reduce code size

C To improve readability and avoid glitches

D To use less memory

Separating output logic improves readability and helps prevent glitches by clearly defining output changes.

Explain the difference between Mealy and Moore FSM output logic and how it affects output timing.

Think about when outputs update relative to inputs and states.

Describe how you would structure a Verilog FSM with output logic for clarity and reliability.

Consider code organization and avoiding glitches.