Blocking vs non-blocking assignment in Verilog - When to Use Which

The Big Idea

Discover how a simple change in assignment style can save your circuit from mysterious bugs!

The Scenario

Imagine you are wiring a complex circuit by hand, connecting each wire one by one, waiting for each connection to finish before starting the next. This slow, step-by-step process makes it hard to build fast and reliable designs.

The Problem

Doing assignments one after another without overlap causes delays and mistakes. If you wait for one signal to update before moving on, your circuit simulation becomes slow and can behave incorrectly, missing how real hardware works in parallel.

The Solution

Using blocking and non-blocking assignments lets you control when signals update. Blocking assignments happen immediately, while non-blocking assignments schedule updates to happen together later. This matches real hardware timing and makes your design clear and efficient.

Before vs After

✗ Before

a = b;
c = a;

✓ After

a <= b;
c <= b;

What It Enables

This concept lets you write hardware designs that behave like real circuits, updating signals in parallel and avoiding timing bugs.

Real Life Example

When designing a digital clock, non-blocking assignments ensure all time registers update simultaneously each tick, preventing wrong time displays.

Key Takeaways

Blocking assignments update signals immediately, one after another.

Non-blocking assignments schedule updates to happen together later.

Choosing the right type helps model real hardware timing and avoid bugs.