Blocking vs non-blocking assignment in Verilog - When to Use Which

The Big Idea

Discover how a simple change in assignment style can save your circuit from mysterious bugs!

The Scenario

Imagine you are wiring a complex circuit by hand, connecting each wire one by one, waiting for each connection to finish before starting the next. This slow, step-by-step process makes it hard to build fast and reliable designs.

The Problem

Doing assignments one after another without overlap causes delays and mistakes. If you wait for one signal to update before moving on, your circuit simulation becomes slow and can behave incorrectly, missing how real hardware works in parallel.

The Solution

Using blocking and non-blocking assignments lets you control when signals update. Blocking assignments happen immediately, while non-blocking assignments schedule updates to happen together later. This matches real hardware timing and makes your design clear and efficient.

Before vs After

✗ Before

a = b;
c = a;

✓ After

a <= b;
c <= b;

What It Enables

This concept lets you write hardware designs that behave like real circuits, updating signals in parallel and avoiding timing bugs.

Real Life Example

When designing a digital clock, non-blocking assignments ensure all time registers update simultaneously each tick, preventing wrong time displays.

Key Takeaways

Blocking assignments update signals immediately, one after another.

Non-blocking assignments schedule updates to happen together later.

Choosing the right type helps model real hardware timing and avoid bugs.

Practice

1. Which of the following statements correctly describes the difference between blocking and non-blocking assignments in Verilog?

easy

A. Blocking assignments are used only in testbenches, non-blocking only in synthesis.

B. Blocking assignments use '<=' and update variables after all right sides are evaluated, while non-blocking assignments use '=' and update variables immediately.

C. Blocking assignments use '=' and update variables immediately, while non-blocking assignments use '<=' and update variables after all right sides are evaluated.

D. Both blocking and non-blocking assignments use '=' but differ in execution speed.

Solution

1. Step 1: Understand blocking assignment behavior

   Blocking assignments use '=' and execute statements in order, updating variables immediately.

2. Step 2: Understand non-blocking assignment behavior

   Non-blocking assignments use '<=' and update variables only after all right-hand sides are evaluated, allowing parallel updates.

3. Final Answer:

   Blocking assignments use '=' and update variables immediately, while non-blocking assignments use '<=' and update variables after all right sides are evaluated. -> Option C

4. Quick Check:

   Blocking = immediate, Non-blocking = delayed update [OK]

Hint: Remember '=' blocks, '<=' schedules update later [OK]

Common Mistakes:

• Confusing '=' and '<=' usage
• Thinking both update variables immediately
• Assuming non-blocking is only for testbenches

2. Which of the following is the correct syntax for a non-blocking assignment in Verilog?

easy

A. reg_var = value;

B. reg_var <= value;

C. reg_var := value;

D. reg_var == value;

Solution

1. Step 1: Identify non-blocking assignment operator

   Non-blocking assignments use the '<=' operator in Verilog.

2. Step 2: Check syntax correctness

   reg_var <= value; uses '<=' correctly, while others use invalid or different operators.

3. Final Answer:

   reg_var <= value; -> Option B

4. Quick Check:

   Non-blocking uses '<=' [OK]

Hint: Non-blocking always uses '<=' operator [OK]

Common Mistakes:

• Using '=' instead of '<=' for non-blocking
• Confusing ':=' or '==' as assignment
• Syntax errors with missing semicolons

3. Consider the following Verilog code snippet inside an always block triggered on the positive edge of clk:

reg a, b, c;
always @(posedge clk) begin
  a = b;
  b <= c;
end

What will be the value of 'a' and 'b' after the clock edge if initially b=0 and c=1?

medium

A. a = 0, b = 1

B. a = 1, b = 1

C. a = 1, b = 0

D. a = 0, b = 0

Solution

1. Step 1: Evaluate blocking assignment 'a = b;'

   Blocking assignment updates 'a' immediately with current 'b' value, which is 0.

2. Step 2: Evaluate non-blocking assignment 'b <= c;'

   Non-blocking assignment schedules 'b' to update after the block with 'c' value, which is 1.

3. Final Answer:

   a = 0, b = 1 -> Option A

4. Quick Check:

   Blocking immediate, non-blocking delayed update [OK]

Hint: Blocking updates now; non-blocking updates after block ends [OK]

Common Mistakes:

• Assuming both update simultaneously
• Confusing initial values of variables
• Ignoring order of assignments

4. Identify the error in the following Verilog code snippet:

always @(posedge clk) begin
  reg1 <= reg2;
  reg2 = reg1;
end

medium

A. Using blocking assignment for reg2 causes incorrect sequential behavior.

B. Non-blocking assignment cannot be used inside always blocks.

C. Missing semicolon after reg2 assignment.

D. reg1 and reg2 must be wires, not regs.

Solution

1. Step 1: Analyze assignment types in sequential block

   In sequential always blocks, non-blocking assignments should be used for all registers to avoid race conditions.

2. Step 2: Identify blocking assignment misuse

   Using blocking assignment '=' for reg2 causes immediate update, which can cause incorrect behavior in sequential logic.

3. Final Answer:

   Using blocking assignment for reg2 causes incorrect sequential behavior. -> Option A

4. Quick Check:

   Sequential logic needs non-blocking assignments [OK]

Hint: Use non-blocking for all regs in sequential blocks [OK]

Common Mistakes:

• Thinking blocking is allowed in sequential always blocks
• Ignoring race conditions caused by mixed assignments
• Assuming wires can be assigned in always blocks

5. You want to model a flip-flop with asynchronous reset in Verilog. Which assignment style correctly models the sequential behavior inside the always block?

always @(posedge clk or posedge reset) begin
  if (reset)
    q = 0;
  else
    q <= d;
end

What is the problem with this code?

hard

A. Reset should use non-blocking '<=' and data should use blocking '=' assignments.

B. The sensitivity list is incorrect; it should not include reset.

C. Both assignments should be blocking '=' for correct flip-flop behavior.

D. Mixing blocking '=' for reset and non-blocking '<=' for data causes simulation mismatches.

Solution

1. Step 1: Understand assignment consistency in sequential blocks

   Sequential logic should use non-blocking assignments consistently to avoid simulation and synthesis mismatches.

2. Step 2: Identify mixed assignment problem

   Using blocking '=' for reset and non-blocking '<=' for data causes timing mismatches and incorrect behavior.

3. Final Answer:

   Mixing blocking '=' for reset and non-blocking '<=' for data causes simulation mismatches. -> Option D

4. Quick Check:

   Use non-blocking consistently in sequential logic [OK]

Hint: Use non-blocking for all sequential assignments including reset [OK]

Common Mistakes:

• Mixing blocking and non-blocking in same always block
• Ignoring asynchronous reset in sensitivity list
• Assuming blocking '=' is fine for reset