Blocking vs non-blocking assignment in Verilog - Quick Revision & Key Differences

Recall & Review

beginner

What is a blocking assignment in Verilog?

A blocking assignment uses the '=' operator and executes statements sequentially, blocking the next statement until the current one finishes.

beginner

What is a non-blocking assignment in Verilog?

A non-blocking assignment uses the '<=' operator and schedules the assignment to happen later, allowing all right-hand side evaluations to complete before updating.

intermediate

When should you use blocking assignments?

Use blocking assignments in combinational logic where statements must execute in order, like simple calculations or if-else conditions.

intermediate

When should you use non-blocking assignments?

Use non-blocking assignments in sequential logic (like inside always blocks triggered by clocks) to model parallel hardware updates correctly.

advanced

What can go wrong if you mix blocking and non-blocking assignments incorrectly?

Mixing them can cause simulation mismatches and unexpected behavior because blocking assignments update immediately, while non-blocking assignments update later.

Which operator is used for blocking assignments in Verilog?

A =>

B <=

C =

D ==

Blocking assignments use the '=' operator to assign values immediately.

Which assignment type schedules updates to happen after all right-hand side evaluations?

A Conditional assignment

B Blocking assignment

C Continuous assignment

D Non-blocking assignment

Non-blocking assignments ('<=') schedule updates to happen later, allowing parallel behavior.

In which type of logic is non-blocking assignment typically used?

A Sequential logic

B Combinational logic

C Testbench code only

D Synthesis directives

Non-blocking assignments are used in sequential logic to model clocked registers.

What happens if you use blocking assignments inside a clocked always block?

A It can cause race conditions and incorrect simulation

B It models hardware registers correctly

C It is ignored by the simulator

D It synthesizes faster hardware

Blocking assignments inside clocked blocks can cause race conditions and simulation mismatches.

Which assignment type updates the variable immediately during simulation?

A Non-blocking assignment

B Blocking assignment

C Continuous assignment

D Procedural assignment

Blocking assignments update the variable immediately, blocking the next statement.

Explain the difference between blocking and non-blocking assignments in Verilog and when to use each.

Think about how hardware updates happen in real circuits.

Describe a potential problem if blocking and non-blocking assignments are mixed incorrectly in a design.

Consider timing of updates during simulation.

Practice

1. Which of the following statements correctly describes the difference between blocking and non-blocking assignments in Verilog?

easy

A. Blocking assignments are used only in testbenches, non-blocking only in synthesis.

B. Blocking assignments use '<=' and update variables after all right sides are evaluated, while non-blocking assignments use '=' and update variables immediately.

C. Blocking assignments use '=' and update variables immediately, while non-blocking assignments use '<=' and update variables after all right sides are evaluated.

D. Both blocking and non-blocking assignments use '=' but differ in execution speed.

Solution

1. Step 1: Understand blocking assignment behavior

   Blocking assignments use '=' and execute statements in order, updating variables immediately.

2. Step 2: Understand non-blocking assignment behavior

   Non-blocking assignments use '<=' and update variables only after all right-hand sides are evaluated, allowing parallel updates.

3. Final Answer:

   Blocking assignments use '=' and update variables immediately, while non-blocking assignments use '<=' and update variables after all right sides are evaluated. -> Option C

4. Quick Check:

   Blocking = immediate, Non-blocking = delayed update [OK]

Hint: Remember '=' blocks, '<=' schedules update later [OK]

Common Mistakes:

• Confusing '=' and '<=' usage
• Thinking both update variables immediately
• Assuming non-blocking is only for testbenches

2. Which of the following is the correct syntax for a non-blocking assignment in Verilog?

easy

A. reg_var = value;

B. reg_var <= value;

C. reg_var := value;

D. reg_var == value;

Solution

1. Step 1: Identify non-blocking assignment operator

   Non-blocking assignments use the '<=' operator in Verilog.

2. Step 2: Check syntax correctness

   reg_var <= value; uses '<=' correctly, while others use invalid or different operators.

3. Final Answer:

   reg_var <= value; -> Option B

4. Quick Check:

   Non-blocking uses '<=' [OK]

Hint: Non-blocking always uses '<=' operator [OK]

Common Mistakes:

• Using '=' instead of '<=' for non-blocking
• Confusing ':=' or '==' as assignment
• Syntax errors with missing semicolons

3. Consider the following Verilog code snippet inside an always block triggered on the positive edge of clk:

reg a, b, c;
always @(posedge clk) begin
  a = b;
  b <= c;
end

What will be the value of 'a' and 'b' after the clock edge if initially b=0 and c=1?

medium

A. a = 0, b = 1

B. a = 1, b = 1

C. a = 1, b = 0

D. a = 0, b = 0

Solution

1. Step 1: Evaluate blocking assignment 'a = b;'

   Blocking assignment updates 'a' immediately with current 'b' value, which is 0.

2. Step 2: Evaluate non-blocking assignment 'b <= c;'

   Non-blocking assignment schedules 'b' to update after the block with 'c' value, which is 1.

3. Final Answer:

   a = 0, b = 1 -> Option A

4. Quick Check:

   Blocking immediate, non-blocking delayed update [OK]

Hint: Blocking updates now; non-blocking updates after block ends [OK]

Common Mistakes:

• Assuming both update simultaneously
• Confusing initial values of variables
• Ignoring order of assignments

4. Identify the error in the following Verilog code snippet:

always @(posedge clk) begin
  reg1 <= reg2;
  reg2 = reg1;
end

medium

A. Using blocking assignment for reg2 causes incorrect sequential behavior.

B. Non-blocking assignment cannot be used inside always blocks.

C. Missing semicolon after reg2 assignment.

D. reg1 and reg2 must be wires, not regs.

Solution

1. Step 1: Analyze assignment types in sequential block

   In sequential always blocks, non-blocking assignments should be used for all registers to avoid race conditions.

2. Step 2: Identify blocking assignment misuse

   Using blocking assignment '=' for reg2 causes immediate update, which can cause incorrect behavior in sequential logic.

3. Final Answer:

   Using blocking assignment for reg2 causes incorrect sequential behavior. -> Option A

4. Quick Check:

   Sequential logic needs non-blocking assignments [OK]

Hint: Use non-blocking for all regs in sequential blocks [OK]

Common Mistakes:

• Thinking blocking is allowed in sequential always blocks
• Ignoring race conditions caused by mixed assignments
• Assuming wires can be assigned in always blocks

5. You want to model a flip-flop with asynchronous reset in Verilog. Which assignment style correctly models the sequential behavior inside the always block?

always @(posedge clk or posedge reset) begin
  if (reset)
    q = 0;
  else
    q <= d;
end

What is the problem with this code?

hard

A. Reset should use non-blocking '<=' and data should use blocking '=' assignments.

B. The sensitivity list is incorrect; it should not include reset.

C. Both assignments should be blocking '=' for correct flip-flop behavior.

D. Mixing blocking '=' for reset and non-blocking '<=' for data causes simulation mismatches.

Solution

1. Step 1: Understand assignment consistency in sequential blocks

   Sequential logic should use non-blocking assignments consistently to avoid simulation and synthesis mismatches.

2. Step 2: Identify mixed assignment problem

   Using blocking '=' for reset and non-blocking '<=' for data causes timing mismatches and incorrect behavior.

3. Final Answer:

   Mixing blocking '=' for reset and non-blocking '<=' for data causes simulation mismatches. -> Option D

4. Quick Check:

   Use non-blocking consistently in sequential logic [OK]

Hint: Use non-blocking for all sequential assignments including reset [OK]

Common Mistakes:

• Mixing blocking and non-blocking in same always block
• Ignoring asynchronous reset in sensitivity list
• Assuming blocking '=' is fine for reset