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Verilogprogramming~10 mins

Blocking vs non-blocking assignment in Verilog - Visual Side-by-Side Comparison

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Concept Flow - Blocking vs non-blocking assignment
Start
Execute blocking (=) assignment
Variable updated immediately
Execute next statement
Execute non-blocking (<=) assignment
Schedule update for end of time step
Execute next statement
At end of time step, update variable
End
Blocking assignments update variables immediately and pause execution; non-blocking assignments schedule updates to happen later, allowing parallel updates.
Execution Sample
Verilog
reg a, b, c;
always @(*) begin
  a = b;      // blocking
  c <= a;     // non-blocking
end
Shows blocking assignment updating 'a' immediately, then non-blocking assignment scheduling 'c' to update after the time step.
Execution Table
StepStatementVariable UpdatedValue BeforeValue AfterNotes
1a = b;a01Blocking assignment updates 'a' immediately to 'b' value (1)
2c <= a;c00 (scheduled)Non-blocking schedules 'c' to update later with current 'a' (1)
3End of time stepc01'c' updated to 'a' value at end of time step
💡 All statements executed; non-blocking assignments update at end of time step
Variable Tracker
VariableStartAfter Step 1After Step 2After Step 3 (End)
a0111
b1111
c000 (scheduled)1
Key Moments - 2 Insights
Why does 'a' change immediately but 'c' does not after their assignments?
Because 'a' uses blocking assignment (=), it updates immediately as shown in step 1 of execution_table. 'c' uses non-blocking (<=), so its update is scheduled and only happens at the end of the time step (step 3).
What happens if we use blocking assignments for both 'a' and 'c'?
Both variables update immediately in order, so 'c' would get the new value of 'a' right away, unlike the non-blocking case where 'c' updates later.
Visual Quiz - 3 Questions
Test your understanding
Look at the execution_table, what is the value of 'a' after step 1?
AUndefined
B0
C1
DScheduled update
💡 Hint
Check the 'Value After' column for 'a' in step 1 of execution_table.
At which step does 'c' actually get its new value?
AStep 3
BStep 1
CStep 2
DNever
💡 Hint
Look at the 'Notes' column for 'c' in execution_table; non-blocking updates happen at end of time step.
If both assignments were blocking, what would happen to 'c' after step 2?
A'c' would remain unchanged
B'c' would update immediately to 'a's new value
C'c' would update at end of time step
D'c' would get 'b's value directly
💡 Hint
Blocking assignments update variables immediately, so 'c' would get 'a's updated value right away.
Concept Snapshot
Blocking assignment (=): updates variable immediately, execution waits.
Non-blocking assignment (<=): schedules update at end of time step, allows parallel updates.
Use blocking for combinational logic, non-blocking for sequential logic.
Order matters for blocking; non-blocking updates happen together after all statements.
Full Transcript
This visual trace shows how blocking and non-blocking assignments work in Verilog. Blocking assignments update variables immediately and pause execution until done. Non-blocking assignments schedule updates to happen later, at the end of the current time step, allowing multiple updates to happen in parallel. In the example, 'a' is assigned from 'b' using blocking, so 'a' changes right away. 'c' is assigned from 'a' using non-blocking, so 'c' keeps its old value during the statements and updates only after all statements finish. This difference is important for writing correct hardware logic.