Blocking vs non-blocking assignment in Verilog - Visual Side-by-Side Comparison

Concept Flow - Blocking vs non-blocking assignment

Start

↓

Execute blocking (=) assignment

↓

Variable updated immediately

↓

Execute next statement

↓

Execute non-blocking (<=) assignment

↓

Schedule update for end of time step

↓

Execute next statement

↓

At end of time step, update variable

↓

End

Blocking assignments update variables immediately and pause execution; non-blocking assignments schedule updates to happen later, allowing parallel updates.

Execution Sample

Verilog

reg a, b, c;
always @(*) begin
  a = b;      // blocking
  c <= a;     // non-blocking
end

Shows blocking assignment updating 'a' immediately, then non-blocking assignment scheduling 'c' to update after the time step.

Execution Table

Step	Statement	Variable Updated	Value Before	Value After	Notes
1	a = b;	a	0	1	Blocking assignment updates 'a' immediately to 'b' value (1)
2	c <= a;	c	0	0 (scheduled)	Non-blocking schedules 'c' to update later with current 'a' (1)
3	End of time step	c	0	1	'c' updated to 'a' value at end of time step

💡 All statements executed; non-blocking assignments update at end of time step

Variable Tracker

Variable	Start	After Step 1	After Step 2	After Step 3 (End)
a	0	1	1	1
b	1	1	1	1
c	0	0	0 (scheduled)	1

Key Moments - 2 Insights

Why does 'a' change immediately but 'c' does not after their assignments?

Because 'a' uses blocking assignment (=), it updates immediately as shown in step 1 of execution_table. 'c' uses non-blocking (<=), so its update is scheduled and only happens at the end of the time step (step 3).

What happens if we use blocking assignments for both 'a' and 'c'?

Both variables update immediately in order, so 'c' would get the new value of 'a' right away, unlike the non-blocking case where 'c' updates later.

Visual Quiz - 3 Questions

Look at the execution_table, what is the value of 'a' after step 1?

A Undefined

B 0

C 1

D Scheduled update

💡 Hint

Check the 'Value After' column for 'a' in step 1 of execution_table.

At which step does 'c' actually get its new value?

A Step 3

B Step 1

C Step 2

D Never

💡 Hint

Look at the 'Notes' column for 'c' in execution_table; non-blocking updates happen at end of time step.

If both assignments were blocking, what would happen to 'c' after step 2?

A 'c' would remain unchanged

B 'c' would update immediately to 'a's new value

C 'c' would update at end of time step

D 'c' would get 'b's value directly

💡 Hint

Blocking assignments update variables immediately, so 'c' would get 'a's updated value right away.

Concept Snapshot

Blocking assignment (=): updates variable immediately, execution waits.
Non-blocking assignment (<=): schedules update at end of time step, allows parallel updates.
Use blocking for combinational logic, non-blocking for sequential logic.
Order matters for blocking; non-blocking updates happen together after all statements.

Full Transcript

This visual trace shows how blocking and non-blocking assignments work in Verilog. Blocking assignments update variables immediately and pause execution until done. Non-blocking assignments schedule updates to happen later, at the end of the current time step, allowing multiple updates to happen in parallel. In the example, 'a' is assigned from 'b' using blocking, so 'a' changes right away. 'c' is assigned from 'a' using non-blocking, so 'c' keeps its old value during the statements and updates only after all statements finish. This difference is important for writing correct hardware logic.

Practice

1. Which of the following statements correctly describes the difference between blocking and non-blocking assignments in Verilog?

easy

A. Blocking assignments are used only in testbenches, non-blocking only in synthesis.

B. Blocking assignments use '<=' and update variables after all right sides are evaluated, while non-blocking assignments use '=' and update variables immediately.

C. Blocking assignments use '=' and update variables immediately, while non-blocking assignments use '<=' and update variables after all right sides are evaluated.

D. Both blocking and non-blocking assignments use '=' but differ in execution speed.

Solution

1. Step 1: Understand blocking assignment behavior

   Blocking assignments use '=' and execute statements in order, updating variables immediately.

2. Step 2: Understand non-blocking assignment behavior

   Non-blocking assignments use '<=' and update variables only after all right-hand sides are evaluated, allowing parallel updates.

3. Final Answer:

   Blocking assignments use '=' and update variables immediately, while non-blocking assignments use '<=' and update variables after all right sides are evaluated. -> Option C

4. Quick Check:

   Blocking = immediate, Non-blocking = delayed update [OK]

Hint: Remember '=' blocks, '<=' schedules update later [OK]

Common Mistakes:

• Confusing '=' and '<=' usage
• Thinking both update variables immediately
• Assuming non-blocking is only for testbenches

2. Which of the following is the correct syntax for a non-blocking assignment in Verilog?

easy

A. reg_var = value;

B. reg_var <= value;

C. reg_var := value;

D. reg_var == value;

Solution

1. Step 1: Identify non-blocking assignment operator

   Non-blocking assignments use the '<=' operator in Verilog.

2. Step 2: Check syntax correctness

   reg_var <= value; uses '<=' correctly, while others use invalid or different operators.

3. Final Answer:

   reg_var <= value; -> Option B

4. Quick Check:

   Non-blocking uses '<=' [OK]

Hint: Non-blocking always uses '<=' operator [OK]

Common Mistakes:

• Using '=' instead of '<=' for non-blocking
• Confusing ':=' or '==' as assignment
• Syntax errors with missing semicolons

3. Consider the following Verilog code snippet inside an always block triggered on the positive edge of clk:

reg a, b, c;
always @(posedge clk) begin
  a = b;
  b <= c;
end

What will be the value of 'a' and 'b' after the clock edge if initially b=0 and c=1?

medium

A. a = 0, b = 1

B. a = 1, b = 1

C. a = 1, b = 0

D. a = 0, b = 0

Solution

1. Step 1: Evaluate blocking assignment 'a = b;'

   Blocking assignment updates 'a' immediately with current 'b' value, which is 0.

2. Step 2: Evaluate non-blocking assignment 'b <= c;'

   Non-blocking assignment schedules 'b' to update after the block with 'c' value, which is 1.

3. Final Answer:

   a = 0, b = 1 -> Option A

4. Quick Check:

   Blocking immediate, non-blocking delayed update [OK]

Hint: Blocking updates now; non-blocking updates after block ends [OK]

Common Mistakes:

• Assuming both update simultaneously
• Confusing initial values of variables
• Ignoring order of assignments

4. Identify the error in the following Verilog code snippet:

always @(posedge clk) begin
  reg1 <= reg2;
  reg2 = reg1;
end

medium

A. Using blocking assignment for reg2 causes incorrect sequential behavior.

B. Non-blocking assignment cannot be used inside always blocks.

C. Missing semicolon after reg2 assignment.

D. reg1 and reg2 must be wires, not regs.

Solution

1. Step 1: Analyze assignment types in sequential block

   In sequential always blocks, non-blocking assignments should be used for all registers to avoid race conditions.

2. Step 2: Identify blocking assignment misuse

   Using blocking assignment '=' for reg2 causes immediate update, which can cause incorrect behavior in sequential logic.

3. Final Answer:

   Using blocking assignment for reg2 causes incorrect sequential behavior. -> Option A

4. Quick Check:

   Sequential logic needs non-blocking assignments [OK]

Hint: Use non-blocking for all regs in sequential blocks [OK]

Common Mistakes:

• Thinking blocking is allowed in sequential always blocks
• Ignoring race conditions caused by mixed assignments
• Assuming wires can be assigned in always blocks

5. You want to model a flip-flop with asynchronous reset in Verilog. Which assignment style correctly models the sequential behavior inside the always block?

always @(posedge clk or posedge reset) begin
  if (reset)
    q = 0;
  else
    q <= d;
end

What is the problem with this code?

hard

A. Reset should use non-blocking '<=' and data should use blocking '=' assignments.

B. The sensitivity list is incorrect; it should not include reset.

C. Both assignments should be blocking '=' for correct flip-flop behavior.

D. Mixing blocking '=' for reset and non-blocking '<=' for data causes simulation mismatches.

Solution

1. Step 1: Understand assignment consistency in sequential blocks

   Sequential logic should use non-blocking assignments consistently to avoid simulation and synthesis mismatches.

2. Step 2: Identify mixed assignment problem

   Using blocking '=' for reset and non-blocking '<=' for data causes timing mismatches and incorrect behavior.

3. Final Answer:

   Mixing blocking '=' for reset and non-blocking '<=' for data causes simulation mismatches. -> Option D

4. Quick Check:

   Use non-blocking consistently in sequential logic [OK]

Hint: Use non-blocking for all sequential assignments including reset [OK]

Common Mistakes:

• Mixing blocking and non-blocking in same always block
• Ignoring asynchronous reset in sensitivity list
• Assuming blocking '=' is fine for reset