Blocking vs non-blocking assignment in Verilog - Practice Questions

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of blocking assignments in sequential statements

What is the output of the following Verilog code snippet after one clock cycle?

reg a, b, c;
always @(posedge clk) begin
  a = 1'b1;
  b = a;
  c = b;
end

Verilog

reg a, b, c;
always @(posedge clk) begin
  a = 1'b1;
  b = a;
  c = b;
end

A a=1, b=1, c=0

B a=0, b=0, c=0

C a=1, b=1, c=1

D a=1, b=0, c=0

💡 Hint

Blocking assignments execute in order and update variables immediately.

Blocking assignments (=) update the variable immediately, so b gets the updated value of a, and c gets the updated value of b in the same clock cycle.

❓ Predict Output

intermediate

Output of non-blocking assignments in sequential statements

What is the output of the following Verilog code snippet after one clock cycle?

reg a, b, c;
always @(posedge clk) begin
  a <= 1'b1;
  b <= a;
  c <= b;
end

Verilog

reg a, b, c;
always @(posedge clk) begin
  a <= 1'b1;
  b <= a;
  c <= b;
end

A a=1, b=0, c=0

B a=1, b=1, c=1

C a=0, b=0, c=0

D a=1, b=1, c=0

💡 Hint

Non-blocking assignments update variables only after the always block finishes.

Non-blocking assignments (<=) schedule updates to happen after the block ends, so b gets the old value of a, and c gets the old value of b.

🔧 Debug

advanced

Identify the error in mixed blocking and non-blocking assignments

Consider this Verilog code inside an always block triggered by posedge clk:

reg x, y;
always @(posedge clk) begin
  x = y;
  y <= x;
end

What problem does this code cause?

Verilog

reg x, y;
always @(posedge clk) begin
  x = y;
  y <= x;
end

A It causes a race condition leading to unpredictable values.

B It causes a syntax error due to mixing assignment types.

C It works correctly and updates x and y as expected.

D It causes a latch to be inferred by synthesis tools.

💡 Hint

Mixing blocking and non-blocking assignments in the same block can cause timing issues.

Using blocking and non-blocking assignments together in the same always block can cause race conditions because blocking assignments update immediately while non-blocking update later.

🧠 Conceptual

advanced

Difference in behavior of blocking vs non-blocking in combinational logic

Which statement best describes the recommended use of blocking and non-blocking assignments in combinational logic always blocks?

A Use a mix of blocking and non-blocking assignments to optimize timing.

B Use non-blocking assignments (<=) because they schedule updates and prevent glitches.

C Avoid both blocking and non-blocking assignments; use continuous assignments instead.

D Use blocking assignments (=) because they update variables immediately and avoid race conditions.

💡 Hint

Combinational logic needs immediate updates to simulate correctly.

Blocking assignments are recommended in combinational always blocks because they update variables immediately, reflecting the combinational logic behavior without race conditions.

❓ Predict Output

expert

Final values after mixed blocking and non-blocking assignments

Given the following Verilog code executed on a posedge clk:

reg a = 0, b = 0;
always @(posedge clk) begin
  a <= b + 1;
  b = a + 1;
end

What are the values of a and b after the clock edge?

Verilog

reg a = 0, b = 0;
always @(posedge clk) begin
  a <= b + 1;
  b = a + 1;
end

A a=0, b=1

B a=1, b=1

C a=1, b=2

D a=2, b=1

💡 Hint

Remember that blocking assignments update immediately, non-blocking update later.

b is assigned immediately with a+1 (a is 0 initially), so b=1. a is scheduled to be b+1 (old b=0), so a=1 after the block ends.