Blocking vs non-blocking assignment in Verilog - Hands-On Comparison

Understanding Blocking vs Non-blocking Assignment in Verilog

📖 Scenario: You are designing a simple digital circuit in Verilog that updates registers based on input signals. Understanding how blocking and non-blocking assignments work will help you predict the circuit's behavior correctly.

🎯 Goal: Build a Verilog module that demonstrates the difference between blocking (=) and non-blocking (<=) assignments by updating registers a, b (blocking), c, d (non-blocking) and observing their values after a clock edge.

📋 What You'll Learn

Create registers a, b, c, d initialized to 0

Create a clock signal clk

Use blocking assignment to update a and b in one always block

Use non-blocking assignment to update c and d in another always block

Display the values of a, b, c, d after updates to observe the difference

💡 Why This Matters

🌍 Real World

Understanding blocking and non-blocking assignments is essential for designing correct synchronous digital circuits and avoiding bugs in hardware description languages like Verilog.

💼 Career

Hardware engineers and FPGA developers must master these concepts to write reliable and predictable RTL code for digital systems.

1

Create registers and clock signal

Create a Verilog module called blocking_nonblocking_demo. Inside it, declare registers a, b, c, d initialized to 0, and a register clk initialized to 0.

Verilog

module blocking_nonblocking_demo();
  // Your code here
endmodule

Need a hint?

Use reg to declare registers and assign initial values with = 0;.

2

Create a clock toggle

Add an always block that toggles the clk signal every 5 time units using #5 clk = ~clk;.

Verilog

module blocking_nonblocking_demo();
  reg a = 0;
  reg b = 0;
  reg c = 0;
  reg d = 0;
  reg clk = 0;

  // Your code here
endmodule

Need a hint?

Use an always block without sensitivity list to create a clock by toggling clk every 5 time units.

3

Add blocking assignment always block

Add an always @(posedge clk) block that updates a and b using blocking assignments: first a = b + 1; then b = a + 1;.

Verilog

module blocking_nonblocking_demo();
  reg a = 0;
  reg b = 0;
  reg c = 0;
  reg d = 0;
  reg clk = 0;

  always begin
    #5 clk = ~clk;
  end

  // Your code here
endmodule

Need a hint?

Use blocking assignments with = inside the always @(posedge clk) block.

4

Add non-blocking assignment always block and display

Add another always @(posedge clk) block that updates c and d using non-blocking assignments: first c <= d + 1; then d <= c + 1;. Also, add an initial block that runs for 30 time units and uses $display to print a, b, c, d every 5 time units.

Verilog

module blocking_nonblocking_demo();
  reg a = 0;
  reg b = 0;
  reg c = 0;
  reg d = 0;
  reg clk = 0;

  always begin
    #5 clk = ~clk;
  end

  always @(posedge clk) begin
    a = b + 1;
    b = a + 1;
  end

  // Your code here
endmodule

Need a hint?

Use non-blocking assignments with <= in a separate always @(posedge clk) block to update c and d. Use initial block with $display and repeat to print values of all registers every 5 time units.