Blocking vs non-blocking assignment in Verilog - Performance Comparison

Time Complexity: Blocking vs non-blocking assignment

O(n)

Understanding Time Complexity

When writing Verilog code, how assignments happen affects how long the code takes to run.

We want to see how blocking and non-blocking assignments change the number of steps the hardware simulation takes.

Scenario Under Consideration

Analyze the time complexity of these two assignment styles.

// Blocking assignment example
always @(posedge clk) begin
  a = b;       // blocking
  c = a + 1;
end

// Non-blocking assignment example
always @(posedge clk) begin
  a <= b;      // non-blocking
  c <= a + 1;
end
    

This code updates signals a and c on a clock edge using two assignment types.

Identify Repeating Operations

Look at what happens every clock cycle.

• Primary operation: Assigning values to signals a and c.
• How many times: Once per clock cycle, but order and timing differ between blocking and non-blocking.

How Execution Grows With Input

Imagine the number of signals grows to n.

Input Size (n)	Approx. Operations
10	10 assignments per cycle
100	100 assignments per cycle
1000	1000 assignments per cycle

Pattern observation: The number of assignments grows linearly with the number of signals.

Final Time Complexity

Time Complexity: O(n)

This means the time to update signals grows directly with how many signals you assign each cycle.

Common Mistake

[X] Wrong: "Blocking assignments always take more time than non-blocking because they run in order."

[OK] Correct: Both assignment types update signals once per cycle; the difference is in timing and simulation order, not the number of operations.

Interview Connect

Understanding how assignment types affect simulation steps helps you write clearer, more predictable hardware code.

Self-Check

"What if we replaced all blocking assignments with non-blocking in a large sequential block? How would the time complexity change?"