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Verilogprogramming~10 mins

Blocking vs non-blocking assignment in Verilog - Interactive Practice

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Practice - 5 Tasks
Answer the questions below
1fill in blank
easy

Complete the code to assign value 1 to signal a using blocking assignment.

Verilog
always @(*) begin
  a [1] 1;
end
Drag options to blanks, or click blank then click option'
A=
B<=
C==
D:=
Attempts:
3 left
💡 Hint
Common Mistakes
Using '<=' instead of '=' for blocking assignment.
2fill in blank
medium

Complete the code to assign value 0 to signal b using non-blocking assignment.

Verilog
always @(posedge clk) begin
  b [1] 0;
end
Drag options to blanks, or click blank then click option'
A:=
B<=
C==
D=
Attempts:
3 left
💡 Hint
Common Mistakes
Using '=' instead of '<=' for non-blocking assignment.
3fill in blank
hard

Fix the error in the code by choosing the correct assignment operator for sequential logic.

Verilog
always @(posedge clk) begin
  c [1] d;
end
Drag options to blanks, or click blank then click option'
A=
B:=
C==
D<=
Attempts:
3 left
💡 Hint
Common Mistakes
Using '=' inside clocked always blocks.
4fill in blank
hard

Fill both blanks to create a combinational block that assigns x to y and z using blocking assignment.

Verilog
always @(*) begin
  y [1] x;
  z [2] y;
end
Drag options to blanks, or click blank then click option'
A=
B<=
C==
D:=
Attempts:
3 left
💡 Hint
Common Mistakes
Mixing blocking and non-blocking assignments in combinational blocks.
5fill in blank
hard

Fill all three blanks to correctly update registers a, b, and c in a clocked block using non-blocking assignments.

Verilog
always @(posedge clk) begin
  a [1] d;
  b [2] a;
  c [3] b;
end
Drag options to blanks, or click blank then click option'
A=
B<=
Attempts:
3 left
💡 Hint
Common Mistakes
Using '=' instead of '<=' in clocked always blocks.
Mixing '=' and '<=' in the same block.