Why Three-block FSM coding style in Verilog? - Purpose & Use Cases

The Big Idea

Discover how splitting your FSM code into three blocks can save hours of debugging frustration!

The Scenario

Imagine trying to design a digital circuit that changes states based on inputs, but you write all the logic in one big block. It quickly becomes a tangled mess where it's hard to track what controls state changes, outputs, or resets.

The Problem

Writing the entire state machine in one block makes the code confusing and error-prone. It's easy to mix up state updates, output logic, and input handling, leading to bugs that are hard to find and fix.

The Solution

The three-block FSM style splits the design into clear parts: one block for state transitions, one for output logic, and one for state registers. This separation makes the design easier to read, debug, and maintain.

Before vs After

✗ Before

always @(posedge clk) begin
  if (reset) state <= IDLE;
  else if (input) state <= NEXT_STATE;
  output = (state == SOME_STATE);
end

✓ After

always @(posedge clk) begin
  if (reset) state <= IDLE;
  else state <= next_state;
end
always @(*) begin
  case(state)
    IDLE: next_state = input ? SOME_STATE : IDLE;
    default: next_state = IDLE;
  endcase
end
always @(*) begin
  output = (state == SOME_STATE);
end

What It Enables

This style lets you build reliable, clear, and scalable state machines that are easy to understand and modify.

Real Life Example

When designing a traffic light controller, using three-block FSM style helps separate timing control, light output signals, and state changes, making the design straightforward and safe.

Key Takeaways

Manual FSM code can get messy and hard to debug.

Three-block FSM style separates state update, next state logic, and output logic.

This separation improves clarity, reduces bugs, and simplifies changes.