Three-block FSM coding style in Verilog - Cheat Sheet & Quick Revision

Recall & Review

beginner

What are the three blocks in the Three-block FSM coding style?

The three blocks are: 1) State register block (holds the current state), 2) Next state logic block (decides the next state based on inputs and current state), 3) Output logic block (generates outputs based on the current state).

beginner

Why do we separate FSM code into three blocks in Verilog?

Separating FSM code into three blocks improves readability, makes debugging easier, and clearly separates state storage, state transitions, and output generation.

beginner

In the Three-block FSM style, which block uses a clock edge to update the state?

The state register block uses the clock edge (usually posedge) to update the current state to the next state.

beginner

What is the role of the next state logic block in the Three-block FSM style?

The next state logic block calculates the next state based on the current state and inputs, without using clock edges.

intermediate

How does the output logic block differ between Moore and Mealy FSMs in the Three-block style?

In Moore FSMs, outputs depend only on the current state and are in the output logic block. In Mealy FSMs, outputs depend on current state and inputs, so output logic block uses both.

Which block in the Three-block FSM style holds the current state?

A State register block

B Next state logic block

C Output logic block

D Input logic block

The state register block stores the current state and updates it on clock edges.

What triggers the update of the current state in the state register block?

A Reset only

B Input change

C Output change

D Clock edge

The current state updates on the clock edge, typically the rising edge.

In the Three-block FSM style, which block decides the next state?

A Output logic block

B Next state logic block

C State register block

D Input register block

The next state logic block computes the next state based on current state and inputs.

Which FSM type has outputs depending only on the current state?

A Mealy FSM

B Both Mealy and Moore

C Moore FSM

D Neither

Moore FSM outputs depend only on the current state.

Why is the Three-block FSM style recommended?

A It separates concerns for clarity and easier debugging

B It mixes state and output logic for speed

C It uses fewer lines of code

D It avoids using clock signals

Separating state register, next state logic, and output logic makes the FSM easier to understand and debug.

Explain the purpose of each of the three blocks in the Three-block FSM coding style.

Think about what happens on clock edges, how next state is decided, and how outputs are created.

Describe how the Three-block FSM style improves code readability and debugging in Verilog.

Consider how dividing tasks helps when reading or fixing code.