Three-block FSM coding style in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple three-block FSM

Consider this three-block FSM code in Verilog. What will be the value of state after 3 clock cycles if reset is initially high and then goes low?

Verilog

module fsm(input clk, input reset, output reg [1:0] state);
  // State encoding
  localparam S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;

  // State register block
  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  // Next state logic block
  reg [1:0] next_state;
  always @(*) begin
    case(state)
      S0: next_state = S1;
      S1: next_state = S2;
      S2: next_state = S0;
      default: next_state = S0;
    endcase
  end

  // Output logic block (not used here)
endmodule

A 2'b00

B 2'b01

C 2'b10

D 2'b11

💡 Hint

Trace the state transitions starting from S0 on reset.

On reset, state is S0 (00). After 1 clock, state moves to S1 (01). After 2 clocks, state moves to S2 (10). After 3 clocks, state moves back to S0 (00).

❓ Predict Output

intermediate

Output of FSM with output logic

Given this three-block FSM, what is the value of out_signal when the FSM is in state S1?

Verilog

module fsm(input clk, input reset, output reg out_signal);
  localparam S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
  reg [1:0] state, next_state;

  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  always @(*) begin
    case(state)
      S0: next_state = S1;
      S1: next_state = S2;
      S2: next_state = S0;
      default: next_state = S0;
    endcase
  end

  always @(*) begin
    case(state)
      S0: out_signal = 1'b0;
      S1: out_signal = 1'b1;
      S2: out_signal = 1'b0;
      default: out_signal = 1'b0;
    endcase
  end
endmodule

A 1'b0

B 1'b1

C High impedance (Z)

D Undefined (X)

💡 Hint

Check the output logic block for state S1.

The output logic block sets out_signal to 1'b1 when the state is S1.

🔧 Debug

advanced

Identify the error in this three-block FSM code

What error will this three-block FSM code produce when compiled?

Verilog

module fsm(input clk, input reset, output reg [1:0] state);
  localparam S0 = 2'b00, S1 = 2'b01;
  reg [1:0] next_state;

  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  always @(*) begin
    case(state)
      S0: next_state = S1;
      S1: next_state = S0;
      default: next_state = S2;
    endcase
  end
endmodule

A TypeError: state and next_state size mismatch

B No error, code compiles fine

C SyntaxError: 'S2' is not declared

D Runtime error: state stuck at S0

💡 Hint

Check the default case in the next state logic.

The code uses S2 in the default case but S2 is not declared anywhere, causing a syntax error.

📝 Syntax

advanced

Which option has correct sensitivity list for next state logic?

In a three-block FSM, the next state logic block should be sensitive to which signals?

A always @(posedge clk)

B always @(state or input_signal)

C always @(posedge clk or posedge reset)

D always @(*)

💡 Hint

Next state logic is combinational logic.

The next state logic block is combinational and should use always @(*) to automatically include all inputs.

🚀 Application

expert

Number of states in a three-block FSM

A three-block FSM uses a 3-bit state register. How many unique states can this FSM represent?

A 8

B 6

C 3

D 16

💡 Hint

Number of states = 2^(number of bits in state register).

A 3-bit register can represent 2^3 = 8 unique states.

Practice

1. In the three-block FSM coding style in Verilog, which block is responsible for storing the current state?

easy

A. The next state combinational logic block

B. The output combinational logic block

C. The state register block using always_ff

D. The reset logic block

Solution

1. Step 1: Understand the role of each FSM block

   The three-block FSM style divides the design into state storage, next state logic, and output logic.

2. Step 2: Identify the block that stores the current state

   The state register block uses always_ff to store the current state in flip-flops.

3. Final Answer:

   The state register block using always_ff -> Option C

4. Quick Check:

   State storage = always_ff block [OK]

Hint: State storage always uses always_ff block [OK]

Common Mistakes:

• Confusing next state logic with state storage
• Thinking output logic stores state
• Mixing combinational and sequential blocks

2. Which of the following is the correct syntax for the next state logic block in a three-block FSM style?

easy

A. always_comb begin next_state = ... end

B. always_ff @(posedge clk) begin next_state = ... end

C. always @(posedge clk or posedge reset) begin state <= next_state; end

D. always @(negedge clk) begin output = ... end

Solution

1. Step 1: Identify the block type for next state logic

   Next state logic is combinational and should use always_comb for clean synthesis and readability.

2. Step 2: Match the syntax with the correct block

   always_comb begin next_state = ... end uses always_comb with next_state assignment, which is correct for next state logic.

3. Final Answer:

   always_comb begin next_state = ... end -> Option A

4. Quick Check:

   Next state logic = always_comb block [OK]

Hint: Next state logic uses always_comb block [OK]

Common Mistakes:

• Using always_ff for next state logic
• Mixing sensitivity lists manually
• Assigning state in next state block

3. Given the following three-block FSM code snippet, what will be the value of state after the rising edge of clk if reset is 0 and current state is 2?

typedef enum logic [1:0] {S0=0, S1=1, S2=2} state_t;

state_t state, next_state;

// State register
always_ff @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else state <= next_state;
end

// Next state logic
always_comb begin
  case(state)
    S0: next_state = S1;
    S1: next_state = S2;
    S2: next_state = S0;
    default: next_state = S0;
  endcase
end

// Output logic (not shown)

medium

A. S0 (0)

B. S1 (1)

C. S2 (2)

D. Reset state

Solution

1. Step 1: Analyze current state and next state logic

   Current state is S2 (2). According to next state logic, from S2 next_state = S0.

2. Step 2: Determine state after clock edge with reset=0

   Since reset=0, state updates to next_state, which is S0 (0).

3. Final Answer:

   S0 (0) -> Option A

4. Quick Check:

   From S2, next_state = S0, so state = S0 after clk [OK]

Hint: Trace next_state from current state, then update on clk [OK]

Common Mistakes:

• Confusing current and next state
• Ignoring reset condition
• Assuming state stays the same

4. Identify the error in this three-block FSM snippet:

always_ff @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else state = next_state;
end

always_comb begin
  case(state)
    S0: next_state = S1;
    S1: next_state = S0;
    default: next_state = S0;
  endcase
end

medium

A. Incorrect case statement syntax

B. Using blocking assignment (=) instead of non-blocking (<=) in always_ff block

C. Missing sensitivity list in always_comb block

D. No reset condition in always_ff block

Solution

1. Step 1: Check assignments in always_ff block

   In sequential blocks (always_ff), non-blocking assignment (<=) must be used to avoid race conditions.

2. Step 2: Identify the incorrect assignment

   The line state = next_state; uses blocking assignment (=), which is incorrect here.

3. Final Answer:

   Using blocking assignment (=) instead of non-blocking (<=) in always_ff block -> Option B

4. Quick Check:

   always_ff requires <= for state updates [OK]

Hint: Use <= in always_ff blocks for state updates [OK]

Common Mistakes:

• Using = instead of <= in sequential blocks
• Forgetting reset condition
• Incorrect sensitivity list in always_comb

5. You want to design a three-block FSM that has an output signal flag which is high only when the FSM is in state S2. Which block should you put the flag assignment in, and what is the correct style?

hard

A. In the reset logic block, assign flag = 0; only

B. In the state register block using always_ff, assign flag <= (state == S2);

C. In the next state logic block using always_comb, assign flag = (next_state == S2);

D. In the output logic block using always_comb, assign flag = (state == S2);

Solution

1. Step 1: Identify where output signals are assigned in three-block FSM

   Output signals based on current state are assigned in the output logic block, which is combinational and uses always_comb.

2. Step 2: Write the correct assignment for flag

   Assign flag = (state == S2); inside the output logic block to reflect current state.

3. Final Answer:

   In the output logic block using always_comb, assign flag = (state == S2); -> Option D

4. Quick Check:

   Output logic uses always_comb with flag = (state == S2) [OK]

Hint: Assign outputs combinationally based on current state [OK]

Common Mistakes:

• Assigning outputs in always_ff block
• Using next_state instead of state for outputs
• Ignoring combinational output logic block