Three-block FSM coding style in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

Output of a simple three-block FSM

Consider this three-block FSM code in Verilog. What will be the value of state after 3 clock cycles if reset is initially high and then goes low?

Verilog

module fsm(input clk, input reset, output reg [1:0] state);
  // State encoding
  localparam S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;

  // State register block
  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  // Next state logic block
  reg [1:0] next_state;
  always @(*) begin
    case(state)
      S0: next_state = S1;
      S1: next_state = S2;
      S2: next_state = S0;
      default: next_state = S0;
    endcase
  end

  // Output logic block (not used here)
endmodule

A 2'b00

B 2'b01

C 2'b10

D 2'b11

💡 Hint

Trace the state transitions starting from S0 on reset.

On reset, state is S0 (00). After 1 clock, state moves to S1 (01). After 2 clocks, state moves to S2 (10). After 3 clocks, state moves back to S0 (00).

❓ Predict Output

intermediate

Output of FSM with output logic

Given this three-block FSM, what is the value of out_signal when the FSM is in state S1?

Verilog

module fsm(input clk, input reset, output reg out_signal);
  localparam S0 = 2'b00, S1 = 2'b01, S2 = 2'b10;
  reg [1:0] state, next_state;

  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  always @(*) begin
    case(state)
      S0: next_state = S1;
      S1: next_state = S2;
      S2: next_state = S0;
      default: next_state = S0;
    endcase
  end

  always @(*) begin
    case(state)
      S0: out_signal = 1'b0;
      S1: out_signal = 1'b1;
      S2: out_signal = 1'b0;
      default: out_signal = 1'b0;
    endcase
  end
endmodule

A 1'b0

B 1'b1

C High impedance (Z)

D Undefined (X)

💡 Hint

Check the output logic block for state S1.

The output logic block sets out_signal to 1'b1 when the state is S1.

🔧 Debug

advanced

Identify the error in this three-block FSM code

What error will this three-block FSM code produce when compiled?

Verilog

module fsm(input clk, input reset, output reg [1:0] state);
  localparam S0 = 2'b00, S1 = 2'b01;
  reg [1:0] next_state;

  always @(posedge clk or posedge reset) begin
    if (reset)
      state <= S0;
    else
      state <= next_state;
  end

  always @(*) begin
    case(state)
      S0: next_state = S1;
      S1: next_state = S0;
      default: next_state = S2;
    endcase
  end
endmodule

A TypeError: state and next_state size mismatch

B No error, code compiles fine

C SyntaxError: 'S2' is not declared

D Runtime error: state stuck at S0

💡 Hint

Check the default case in the next state logic.

The code uses S2 in the default case but S2 is not declared anywhere, causing a syntax error.

📝 Syntax

advanced

Which option has correct sensitivity list for next state logic?

In a three-block FSM, the next state logic block should be sensitive to which signals?

A always @(posedge clk)

B always @(state or input_signal)

C always @(posedge clk or posedge reset)

D always @(*)

💡 Hint

Next state logic is combinational logic.

The next state logic block is combinational and should use always @(*) to automatically include all inputs.

🚀 Application

expert

Number of states in a three-block FSM

A three-block FSM uses a 3-bit state register. How many unique states can this FSM represent?

A 8

B 6

C 3

D 16

💡 Hint

Number of states = 2^(number of bits in state register).

A 3-bit register can represent 2^3 = 8 unique states.