Three-block FSM coding style in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the state register in the FSM.

Verilog

reg [1] ;

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Astate

Bclk

Creset

Dinput_signal

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or reset as the state register name.

Forgetting to declare the state register.

The state register holds the current state of the FSM.

2fill in blank

medium

Complete the code to define the next state logic in the FSM.

Verilog

always @(*) begin
  case (state)
    IDLE: next_state = [1];
    default: next_state = IDLE;
  endcase
end

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ASTART

Bclk

Creset

Dinput_signal

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning signals like clock or reset as next state.

Using undefined state names.

The next state after IDLE is usually START or another defined state.

3fill in blank

hard

Fix the error in the state update block by completing the sensitivity list.

Verilog

always @(posedge clk or posedge [1]) begin
  if (reset) state <= IDLE;
  else state <= next_state;
end

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Aenable

Breset

Cinput_signal

Dstart

Attempts:

3 left

💡 Hint

Common Mistakes

Using signals other than reset in the sensitivity list.

Omitting reset from the sensitivity list.

The reset signal is usually asynchronous and included in the sensitivity list.

4fill in blank

hard

Fill both blanks to complete the output logic block for the FSM.

Verilog

always @(*) begin
  case (state)
    IDLE: output_signal = [1];
    START: output_signal = [2];
    default: output_signal = 0;
  endcase
end

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A0

B1

Cenable

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using signals like enable or reset as output values.

Assigning outputs incorrectly for states.

Outputs depend on the current state; IDLE usually outputs 0, START outputs 1.

5fill in blank

hard

Fill all three blanks to complete the three-block FSM style: state register, next state logic, and output logic.

Verilog

reg [1];
reg [2];

always @(posedge clk or posedge reset) begin
  if (reset) [1] <= IDLE;
  else [1] <= [2];
end

always @(*) begin
  case ([3])
    IDLE: [2] = START;
    START: [2] = IDLE;
    default: [2] = IDLE;
  endcase
end

always @(*) begin
  output_signal = 0;
  case ([3])
    START: output_signal = 1;
  endcase
end

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Astate

Bnext_state

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock as a variable in the FSM logic.

Mixing up state and next_state variables.

The state register is state, the next state variable is next_state, and the case uses state.