Three-block FSM coding style in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to declare the state register in the FSM.

Verilog

reg [1] ;

Drag options to blanks, or click blank then click option'

Astate

Bclk

Creset

Dinput_signal

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock or reset as the state register name.

Forgetting to declare the state register.

The state register holds the current state of the FSM.

2fill in blank

medium

Complete the code to define the next state logic in the FSM.

Verilog

always @(*) begin
  case (state)
    IDLE: next_state = [1];
    default: next_state = IDLE;
  endcase
end

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ASTART

Bclk

Creset

Dinput_signal

Attempts:

3 left

💡 Hint

Common Mistakes

Assigning signals like clock or reset as next state.

Using undefined state names.

The next state after IDLE is usually START or another defined state.

3fill in blank

hard

Fix the error in the state update block by completing the sensitivity list.

Verilog

always @(posedge clk or posedge [1]) begin
  if (reset) state <= IDLE;
  else state <= next_state;
end

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Aenable

Breset

Cinput_signal

Dstart

Attempts:

3 left

💡 Hint

Common Mistakes

Using signals other than reset in the sensitivity list.

Omitting reset from the sensitivity list.

The reset signal is usually asynchronous and included in the sensitivity list.

4fill in blank

hard

Fill both blanks to complete the output logic block for the FSM.

Verilog

always @(*) begin
  case (state)
    IDLE: output_signal = [1];
    START: output_signal = [2];
    default: output_signal = 0;
  endcase
end

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A0

B1

Cenable

Dreset

Attempts:

3 left

💡 Hint

Common Mistakes

Using signals like enable or reset as output values.

Assigning outputs incorrectly for states.

Outputs depend on the current state; IDLE usually outputs 0, START outputs 1.

5fill in blank

hard

Fill all three blanks to complete the three-block FSM style: state register, next state logic, and output logic.

Verilog

reg [1];
reg [2];

always @(posedge clk or posedge reset) begin
  if (reset) [1] <= IDLE;
  else [1] <= [2];
end

always @(*) begin
  case ([3])
    IDLE: [2] = START;
    START: [2] = IDLE;
    default: [2] = IDLE;
  endcase
end

always @(*) begin
  output_signal = 0;
  case ([3])
    START: output_signal = 1;
  endcase
end

Drag options to blanks, or click blank then click option'

Astate

Bnext_state

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock as a variable in the FSM logic.

Mixing up state and next_state variables.

The state register is state, the next state variable is next_state, and the case uses state.

Practice

1. In the three-block FSM coding style in Verilog, which block is responsible for storing the current state?

easy

A. The next state combinational logic block

B. The output combinational logic block

C. The state register block using always_ff

D. The reset logic block

Solution

1. Step 1: Understand the role of each FSM block

   The three-block FSM style divides the design into state storage, next state logic, and output logic.

2. Step 2: Identify the block that stores the current state

   The state register block uses always_ff to store the current state in flip-flops.

3. Final Answer:

   The state register block using always_ff -> Option C

4. Quick Check:

   State storage = always_ff block [OK]

Hint: State storage always uses always_ff block [OK]

Common Mistakes:

• Confusing next state logic with state storage
• Thinking output logic stores state
• Mixing combinational and sequential blocks

2. Which of the following is the correct syntax for the next state logic block in a three-block FSM style?

easy

A. always_comb begin next_state = ... end

B. always_ff @(posedge clk) begin next_state = ... end

C. always @(posedge clk or posedge reset) begin state <= next_state; end

D. always @(negedge clk) begin output = ... end

Solution

1. Step 1: Identify the block type for next state logic

   Next state logic is combinational and should use always_comb for clean synthesis and readability.

2. Step 2: Match the syntax with the correct block

   always_comb begin next_state = ... end uses always_comb with next_state assignment, which is correct for next state logic.

3. Final Answer:

   always_comb begin next_state = ... end -> Option A

4. Quick Check:

   Next state logic = always_comb block [OK]

Hint: Next state logic uses always_comb block [OK]

Common Mistakes:

• Using always_ff for next state logic
• Mixing sensitivity lists manually
• Assigning state in next state block

3. Given the following three-block FSM code snippet, what will be the value of state after the rising edge of clk if reset is 0 and current state is 2?

typedef enum logic [1:0] {S0=0, S1=1, S2=2} state_t;

state_t state, next_state;

// State register
always_ff @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else state <= next_state;
end

// Next state logic
always_comb begin
  case(state)
    S0: next_state = S1;
    S1: next_state = S2;
    S2: next_state = S0;
    default: next_state = S0;
  endcase
end

// Output logic (not shown)

medium

A. S0 (0)

B. S1 (1)

C. S2 (2)

D. Reset state

Solution

1. Step 1: Analyze current state and next state logic

   Current state is S2 (2). According to next state logic, from S2 next_state = S0.

2. Step 2: Determine state after clock edge with reset=0

   Since reset=0, state updates to next_state, which is S0 (0).

3. Final Answer:

   S0 (0) -> Option A

4. Quick Check:

   From S2, next_state = S0, so state = S0 after clk [OK]

Hint: Trace next_state from current state, then update on clk [OK]

Common Mistakes:

• Confusing current and next state
• Ignoring reset condition
• Assuming state stays the same

4. Identify the error in this three-block FSM snippet:

always_ff @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else state = next_state;
end

always_comb begin
  case(state)
    S0: next_state = S1;
    S1: next_state = S0;
    default: next_state = S0;
  endcase
end

medium

A. Incorrect case statement syntax

B. Using blocking assignment (=) instead of non-blocking (<=) in always_ff block

C. Missing sensitivity list in always_comb block

D. No reset condition in always_ff block

Solution

1. Step 1: Check assignments in always_ff block

   In sequential blocks (always_ff), non-blocking assignment (<=) must be used to avoid race conditions.

2. Step 2: Identify the incorrect assignment

   The line state = next_state; uses blocking assignment (=), which is incorrect here.

3. Final Answer:

   Using blocking assignment (=) instead of non-blocking (<=) in always_ff block -> Option B

4. Quick Check:

   always_ff requires <= for state updates [OK]

Hint: Use <= in always_ff blocks for state updates [OK]

Common Mistakes:

• Using = instead of <= in sequential blocks
• Forgetting reset condition
• Incorrect sensitivity list in always_comb

5. You want to design a three-block FSM that has an output signal flag which is high only when the FSM is in state S2. Which block should you put the flag assignment in, and what is the correct style?

hard

A. In the reset logic block, assign flag = 0; only

B. In the state register block using always_ff, assign flag <= (state == S2);

C. In the next state logic block using always_comb, assign flag = (next_state == S2);

D. In the output logic block using always_comb, assign flag = (state == S2);

Solution

1. Step 1: Identify where output signals are assigned in three-block FSM

   Output signals based on current state are assigned in the output logic block, which is combinational and uses always_comb.

2. Step 2: Write the correct assignment for flag

   Assign flag = (state == S2); inside the output logic block to reflect current state.

3. Final Answer:

   In the output logic block using always_comb, assign flag = (state == S2); -> Option D

4. Quick Check:

   Output logic uses always_comb with flag = (state == S2) [OK]

Hint: Assign outputs combinationally based on current state [OK]

Common Mistakes:

• Assigning outputs in always_ff block
• Using next_state instead of state for outputs
• Ignoring combinational output logic block