Three-block FSM coding style in Verilog - Step-by-Step Execution

Concept Flow - Three-block FSM coding style

Input Signals

↓

Combinational Logic

↓

State Register

↓

Output Signals

↩Loop back from State Register to Combinational Logic for next cycle

The three-block FSM style separates the design into input processing, next state logic, and state updating, making the design clear and easy to follow.

Execution Sample

Verilog

always_comb begin
  case(state)
    IDLE: if(start) next_state = BUSY; else next_state = IDLE;
    BUSY: if(done) next_state = IDLE; else next_state = BUSY;
  endcase
end

This code block decides the next state based on the current state and inputs.

Execution Table

Step	Current State	Input start	Input done	Next State	Output	Action
1	IDLE	0	0	IDLE	0	No start, stay IDLE
2	IDLE	1	0	BUSY	0	Start signal received, move to BUSY
3	BUSY	1	0	BUSY	1	Busy, not done, stay BUSY
4	BUSY	1	1	IDLE	1	Done signal received, go to IDLE
5	IDLE	0	1	IDLE	0	No start, stay IDLE
6	IDLE	0	0	IDLE	0	No start, stay IDLE

💡 FSM runs continuously, state updates each clock cycle based on inputs

Variable Tracker

Variable	Start	After 1	After 2	After 3	After 4	After 5	Final
state	IDLE	IDLE	BUSY	BUSY	IDLE	IDLE	IDLE
next_state	X	IDLE	BUSY	BUSY	IDLE	IDLE	IDLE
output	0	0	1	1	0	0	0

Key Moments - 3 Insights

Why do we separate next state logic from the state register?

Separating next state logic (combinational) from the state register (sequential) avoids mixing timing and logic, making the FSM predictable and easier to debug, as shown in the execution_table where next_state is decided before updating state.

What happens if we forget to update the state register on the clock edge?

If the state register is not updated on the clock edge, the FSM will never change states, staying stuck in the initial state, as would be seen if 'state' never changes in variable_tracker.

Why do outputs depend on the current state and not the next state?

Outputs depend on the current state to ensure stable and synchronous behavior during the clock cycle, as the output in execution_table matches the current state, not the next_state.

Visual Quiz - 3 Questions

Look at the execution_table at Step 2. What is the next_state when start=1 and current state is IDLE?

A BUSY

B IDLE

C DONE

D ERROR

💡 Hint

Check the 'Next State' column at Step 2 in execution_table.

At which step does the FSM return to IDLE after being BUSY?

A Step 3

B Step 5

C Step 4

D Step 6

💡 Hint

Look for when 'Current State' is BUSY and 'Next State' changes to IDLE in execution_table.

If the input 'done' never becomes 1, what will happen to the state in variable_tracker?

A State will keep toggling between IDLE and BUSY

B State will stay in BUSY forever

C State will stay in IDLE forever

D State will become ERROR

💡 Hint

Check variable_tracker rows for 'state' and how it changes when 'done' is 0.

Concept Snapshot

Three-block FSM style:
1. Combinational block: decides next_state and outputs from current state and inputs.
2. Sequential block: updates current state on clock edge.
3. Output block: outputs depend on current state.
Separates logic for clarity and reliable timing.

Full Transcript

This visual execution shows the three-block FSM coding style in Verilog. The FSM has three parts: combinational logic to decide the next state and outputs, a state register updated on the clock edge, and outputs based on the current state. The execution table traces the FSM through six steps, showing how inputs 'start' and 'done' affect the next state and output. The variable tracker shows how 'state', 'next_state', and 'output' change over time. Key moments clarify why separating next state logic and state register is important, and why outputs depend on the current state. The quiz tests understanding of state transitions and behavior when inputs change. This style helps beginners write clear, predictable FSMs.