Three-block FSM coding style in Verilog - Mini Project: Build & Apply

Three-block FSM coding style

📖 Scenario: You are designing a simple traffic light controller using a three-block FSM style in Verilog. The traffic light cycles through three states: Green, Yellow, and Red. Each state lasts for a fixed number of clock cycles.

🎯 Goal: Build a three-block FSM in Verilog with separate blocks for state register, next state logic, and output logic to control the traffic light signals.

📋 What You'll Learn

Create a state register block with a clock and reset

Create a combinational block for next state logic using case statement

Create a combinational block for output logic based on current state

Use three states: GREEN, YELLOW, and RED

Print the current state name in the final output step

💡 Why This Matters

🌍 Real World

Traffic light controllers use FSMs to manage light changes safely and predictably.

💼 Career

Understanding three-block FSM style is essential for hardware design engineers working with digital circuits and FPGA/ASIC development.

1

Define states and state register

Define a typedef enum logic [1:0] called state_t with states GREEN = 2'b00, YELLOW = 2'b01, and RED = 2'b10. Then create a state_reg register of type state_t and a synchronous reset that sets state_reg to GREEN on reset.

Verilog

// Define state_t enum and state_reg with reset
// Your code here

Need a hint?

Use typedef enum logic [1:0] to define states. Use always_ff block for state register with reset.

2

Write next state logic

Create a combinational always_comb block that sets state_next based on state_reg. Use a case statement: from GREEN go to YELLOW, from YELLOW go to RED, and from RED go back to GREEN.

Verilog

typedef enum logic [1:0] {
    GREEN = 2'b00,
    YELLOW = 2'b01,
    RED = 2'b10
} state_t;

state_t state_reg, state_next;
always_ff @(posedge clk or posedge reset) begin
    if (reset)
        state_reg <= GREEN;
    else
        state_reg <= state_next;
end

// Add always_comb block for next state logic
// Your code here

Need a hint?

Use always_comb and case to assign state_next based on state_reg.

3

Create output logic for traffic lights

Create a combinational always_comb block that sets three output signals: green_light, yellow_light, and red_light based on state_reg. Turn on only the light corresponding to the current state and turn off the others.

Verilog

typedef enum logic [1:0] {
    GREEN = 2'b00,
    YELLOW = 2'b01,
    RED = 2'b10
} state_t;

state_t state_reg, state_next;
always_ff @(posedge clk or posedge reset) begin
    if (reset)
        state_reg <= GREEN;
    else
        state_reg <= state_next;
end

always_comb begin
    case (state_reg)
        GREEN: state_next = YELLOW;
        YELLOW: state_next = RED;
        RED: state_next = GREEN;
        default: state_next = GREEN;
    endcase
end

// Define output signals
logic green_light;
logic yellow_light;
logic red_light;

// Your code here

Need a hint?

Initialize all lights to 0, then turn on the one matching state_reg.

4

Print current state name

Add a always_ff @(posedge clk) block that prints the current state name ("GREEN", "YELLOW", or "RED") using $display whenever the state changes.

Verilog

typedef enum logic [1:0] {
    GREEN = 2'b00,
    YELLOW = 2'b01,
    RED = 2'b10
} state_t;

state_t state_reg, state_next;
always_ff @(posedge clk or posedge reset) begin
    if (reset)
        state_reg <= GREEN;
    else
        state_reg <= state_next;
end

always_comb begin
    case (state_reg)
        GREEN: state_next = YELLOW;
        YELLOW: state_next = RED;
        RED: state_next = GREEN;
        default: state_next = GREEN;
    endcase
end

logic green_light;
logic yellow_light;
logic red_light;
always_comb begin
    green_light = 0;
    yellow_light = 0;
    red_light = 0;
    case (state_reg)
        GREEN: green_light = 1;
        YELLOW: yellow_light = 1;
        RED: red_light = 1;
    endcase
end

// Your code here

Need a hint?

Use always_ff @(posedge clk) and $display to print the state name.