Three-block FSM coding style in Verilog - Mini Project: Build & Apply

Three-block FSM coding style

📖 Scenario: You are designing a simple traffic light controller using a three-block FSM style in Verilog. The traffic light cycles through three states: Green, Yellow, and Red. Each state lasts for a fixed number of clock cycles.

🎯 Goal: Build a three-block FSM in Verilog with separate blocks for state register, next state logic, and output logic to control the traffic light signals.

📋 What You'll Learn

Create a state register block with a clock and reset

Create a combinational block for next state logic using case statement

Create a combinational block for output logic based on current state

Use three states: GREEN, YELLOW, and RED

Print the current state name in the final output step

💡 Why This Matters

🌍 Real World

Traffic light controllers use FSMs to manage light changes safely and predictably.

💼 Career

Understanding three-block FSM style is essential for hardware design engineers working with digital circuits and FPGA/ASIC development.

1

Define states and state register

Define a typedef enum logic [1:0] called state_t with states GREEN = 2'b00, YELLOW = 2'b01, and RED = 2'b10. Then create a state_reg register of type state_t and a synchronous reset that sets state_reg to GREEN on reset.

Verilog

// Define state_t enum and state_reg with reset
// Your code here

Hint

Use typedef enum logic [1:0] to define states. Use always_ff block for state register with reset.

2

Write next state logic

Create a combinational always_comb block that sets state_next based on state_reg. Use a case statement: from GREEN go to YELLOW, from YELLOW go to RED, and from RED go back to GREEN.

Verilog

typedef enum logic [1:0] {
    GREEN = 2'b00,
    YELLOW = 2'b01,
    RED = 2'b10
} state_t;

state_t state_reg, state_next;
always_ff @(posedge clk or posedge reset) begin
    if (reset)
        state_reg <= GREEN;
    else
        state_reg <= state_next;
end

// Add always_comb block for next state logic
// Your code here

Hint

Use always_comb and case to assign state_next based on state_reg.

3

Create output logic for traffic lights

Create a combinational always_comb block that sets three output signals: green_light, yellow_light, and red_light based on state_reg. Turn on only the light corresponding to the current state and turn off the others.

Verilog

typedef enum logic [1:0] {
    GREEN = 2'b00,
    YELLOW = 2'b01,
    RED = 2'b10
} state_t;

state_t state_reg, state_next;
always_ff @(posedge clk or posedge reset) begin
    if (reset)
        state_reg <= GREEN;
    else
        state_reg <= state_next;
end

always_comb begin
    case (state_reg)
        GREEN: state_next = YELLOW;
        YELLOW: state_next = RED;
        RED: state_next = GREEN;
        default: state_next = GREEN;
    endcase
end

// Define output signals
logic green_light;
logic yellow_light;
logic red_light;

// Your code here

Hint

Initialize all lights to 0, then turn on the one matching state_reg.

4

Print current state name

Add a always_ff @(posedge clk) block that prints the current state name ("GREEN", "YELLOW", or "RED") using $display whenever the state changes.

Verilog

typedef enum logic [1:0] {
    GREEN = 2'b00,
    YELLOW = 2'b01,
    RED = 2'b10
} state_t;

state_t state_reg, state_next;
always_ff @(posedge clk or posedge reset) begin
    if (reset)
        state_reg <= GREEN;
    else
        state_reg <= state_next;
end

always_comb begin
    case (state_reg)
        GREEN: state_next = YELLOW;
        YELLOW: state_next = RED;
        RED: state_next = GREEN;
        default: state_next = GREEN;
    endcase
end

logic green_light;
logic yellow_light;
logic red_light;
always_comb begin
    green_light = 0;
    yellow_light = 0;
    red_light = 0;
    case (state_reg)
        GREEN: green_light = 1;
        YELLOW: yellow_light = 1;
        RED: red_light = 1;
    endcase
end

// Your code here

Hint

Use always_ff @(posedge clk) and $display to print the state name.

Practice

1. In the three-block FSM coding style in Verilog, which block is responsible for storing the current state?

easy

A. The next state combinational logic block

B. The output combinational logic block

C. The state register block using always_ff

D. The reset logic block

Solution

1. Step 1: Understand the role of each FSM block

   The three-block FSM style divides the design into state storage, next state logic, and output logic.

2. Step 2: Identify the block that stores the current state

   The state register block uses always_ff to store the current state in flip-flops.

3. Final Answer:

   The state register block using always_ff -> Option C

4. Quick Check:

   State storage = always_ff block [OK]

Hint: State storage always uses always_ff block [OK]

Common Mistakes:

• Confusing next state logic with state storage
• Thinking output logic stores state
• Mixing combinational and sequential blocks

2. Which of the following is the correct syntax for the next state logic block in a three-block FSM style?

easy

A. always_comb begin next_state = ... end

B. always_ff @(posedge clk) begin next_state = ... end

C. always @(posedge clk or posedge reset) begin state <= next_state; end

D. always @(negedge clk) begin output = ... end

Solution

1. Step 1: Identify the block type for next state logic

   Next state logic is combinational and should use always_comb for clean synthesis and readability.

2. Step 2: Match the syntax with the correct block

   always_comb begin next_state = ... end uses always_comb with next_state assignment, which is correct for next state logic.

3. Final Answer:

   always_comb begin next_state = ... end -> Option A

4. Quick Check:

   Next state logic = always_comb block [OK]

Hint: Next state logic uses always_comb block [OK]

Common Mistakes:

• Using always_ff for next state logic
• Mixing sensitivity lists manually
• Assigning state in next state block

3. Given the following three-block FSM code snippet, what will be the value of state after the rising edge of clk if reset is 0 and current state is 2?

typedef enum logic [1:0] {S0=0, S1=1, S2=2} state_t;

state_t state, next_state;

// State register
always_ff @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else state <= next_state;
end

// Next state logic
always_comb begin
  case(state)
    S0: next_state = S1;
    S1: next_state = S2;
    S2: next_state = S0;
    default: next_state = S0;
  endcase
end

// Output logic (not shown)

medium

A. S0 (0)

B. S1 (1)

C. S2 (2)

D. Reset state

Solution

1. Step 1: Analyze current state and next state logic

   Current state is S2 (2). According to next state logic, from S2 next_state = S0.

2. Step 2: Determine state after clock edge with reset=0

   Since reset=0, state updates to next_state, which is S0 (0).

3. Final Answer:

   S0 (0) -> Option A

4. Quick Check:

   From S2, next_state = S0, so state = S0 after clk [OK]

Hint: Trace next_state from current state, then update on clk [OK]

Common Mistakes:

• Confusing current and next state
• Ignoring reset condition
• Assuming state stays the same

4. Identify the error in this three-block FSM snippet:

always_ff @(posedge clk or posedge reset) begin
  if (reset) state <= S0;
  else state = next_state;
end

always_comb begin
  case(state)
    S0: next_state = S1;
    S1: next_state = S0;
    default: next_state = S0;
  endcase
end

medium

A. Incorrect case statement syntax

B. Using blocking assignment (=) instead of non-blocking (<=) in always_ff block

C. Missing sensitivity list in always_comb block

D. No reset condition in always_ff block

Solution

1. Step 1: Check assignments in always_ff block

   In sequential blocks (always_ff), non-blocking assignment (<=) must be used to avoid race conditions.

2. Step 2: Identify the incorrect assignment

   The line state = next_state; uses blocking assignment (=), which is incorrect here.

3. Final Answer:

   Using blocking assignment (=) instead of non-blocking (<=) in always_ff block -> Option B

4. Quick Check:

   always_ff requires <= for state updates [OK]

Hint: Use <= in always_ff blocks for state updates [OK]

Common Mistakes:

• Using = instead of <= in sequential blocks
• Forgetting reset condition
• Incorrect sensitivity list in always_comb

5. You want to design a three-block FSM that has an output signal flag which is high only when the FSM is in state S2. Which block should you put the flag assignment in, and what is the correct style?

hard

A. In the reset logic block, assign flag = 0; only

B. In the state register block using always_ff, assign flag <= (state == S2);

C. In the next state logic block using always_comb, assign flag = (next_state == S2);

D. In the output logic block using always_comb, assign flag = (state == S2);

Solution

1. Step 1: Identify where output signals are assigned in three-block FSM

   Output signals based on current state are assigned in the output logic block, which is combinational and uses always_comb.

2. Step 2: Write the correct assignment for flag

   Assign flag = (state == S2); inside the output logic block to reflect current state.

3. Final Answer:

   In the output logic block using always_comb, assign flag = (state == S2); -> Option D

4. Quick Check:

   Output logic uses always_comb with flag = (state == S2) [OK]

Hint: Assign outputs combinationally based on current state [OK]

Common Mistakes:

• Assigning outputs in always_ff block
• Using next_state instead of state for outputs
• Ignoring combinational output logic block