Latch inference and how to avoid it in Verilog - Step-by-Step Execution

Concept Flow - Latch inference and how to avoid it

Start always block

↓

Check if-else conditions

↓

Is output assigned in all branches?

No→Latch inferred

Yes↓

Output assigned in all cases

↓

No latch inferred

↓

End always block

The flow shows how missing assignments in some branches cause latch inference, and assigning outputs in all branches avoids it.

Execution Sample

Verilog

always @(*) begin
  if (enable)
    out = in;
  // missing else assignment
end

This code infers a latch because 'out' is not assigned when 'enable' is false.

Execution Table

Step	Condition (enable)	Output assigned?	Action	Latch inferred?
1	enable = 1	Yes (out = in)	Assign out = in	No
2	enable = 0	No	No assignment to out	Yes (latch inferred)
3	End	-	-	Stop: latch inferred due to missing assignment

💡 Latch inferred because output 'out' is not assigned when enable is 0

Variable Tracker

Variable	Start	After Step 1	After Step 2	Final
out	undefined	in (when enable=1)	retains previous value (when enable=0)	retains previous value (latch)

Key Moments - 2 Insights

Why does missing an else branch cause a latch?

Because in step 2 of the execution_table, when enable=0, 'out' is not assigned, so the hardware remembers the previous value, creating a latch.

How to avoid latch inference in combinational always blocks?

Assign the output variable in every possible branch, including else, so no value is left unassigned as shown in step 1 and 2.

Visual Quiz - 3 Questions

Look at the execution_table, what happens to 'out' when enable is 0?

A 'out' keeps its previous value (latch behavior)

B 'out' is assigned to zero

C 'out' is assigned to 'in'

D 'out' becomes undefined

💡 Hint

Check step 2 in execution_table where enable=0 and output is not assigned

At which step does the latch get inferred according to the execution_table?

A Step 1

B Step 3

C Step 2

D No latch inferred

💡 Hint

Look at the 'Latch inferred?' column in execution_table

If we add an else branch assigning 'out = 0', how does the execution_table change?

A Latch inference still occurs at step 2

B Latch inference is avoided; 'out' assigned in all steps

C 'out' becomes undefined at step 1

D No change in latch inference

💡 Hint

Think about assigning 'out' in all branches to avoid latch as explained in key_moments

Concept Snapshot

Latch inference happens when outputs are not assigned in all branches of combinational always blocks.
To avoid latches, always assign outputs in every if-else branch.
Missing assignments cause hardware to remember previous values (latch).
Use default assignments or else branches to cover all cases.
This ensures combinational logic without unintended memory.

Full Transcript

Latch inference in Verilog occurs when an output variable inside a combinational always block is not assigned in all possible branches of the code. For example, if an if statement assigns a value to an output when a condition is true but there is no else branch assigning the output when the condition is false, the hardware infers a latch to remember the previous value. This is because the output must hold its value when not explicitly assigned. The execution table shows that when enable is 1, the output is assigned, but when enable is 0, the output is not assigned, causing latch inference. To avoid this, always assign the output in every branch, including else, or provide a default assignment at the start of the always block. This practice ensures the output is always driven and no latch is created. Understanding this helps write correct combinational logic without unintended memory elements.

Practice

1. What causes latch inference in Verilog combinational blocks?

easy

A. Assigning default values to outputs

B. Using clocked always blocks

C. Using non-blocking assignments

D. Not assigning output signals in all possible conditions

Solution

1. Step 1: Understand latch inference context

   Latch inference occurs when outputs inside combinational blocks are not assigned in every possible condition.

2. Step 2: Identify cause of latch inference

   If an output is missing assignment in some branches, Verilog infers a latch to hold the previous value.

3. Final Answer:

   Not assigning output signals in all possible conditions -> Option D

4. Quick Check:

   Missing assignments cause latch inference [OK]

Hint: Always assign outputs in every condition to avoid latches [OK]

Common Mistakes:

• Thinking clocked blocks cause latch inference
• Believing non-blocking assignments cause latches
• Ignoring missing else branches

2. Which Verilog code snippet correctly avoids latch inference in a combinational block?

easy

A. always @(*) begin
out = 0;
if (sel) out = 1;
end

B. always @(*) begin
if (sel) out = 1;
end

C. always @(posedge clk) begin
if (sel) out <= 1;
end

D. always @(*) begin
if (sel) out = 1;
else if (sel) out = 0;
end

Solution

1. Step 1: Check for default assignment

   always @(*) begin out = 0; if (sel) out = 1; end assigns a default value to 'out' before conditional checks, preventing latch inference.

2. Step 2: Compare other options

   always @(*) begin if (sel) out = 1; end misses assignment when 'sel' is false, causing latch. always @(posedge clk) begin if (sel) out <= 1; end is clocked, not combinational. always @(*) begin if (sel) out = 1; else if (sel) out = 0; end misses assignment when 'sel' is false since both conditions require sel true, causing latch.

3. Final Answer:

   Assigning default value before conditions to avoid latches -> Option A

4. Quick Check:

   Default assignment prevents latch [OK]

Hint: Assign default output values at start of combinational blocks [OK]

Common Mistakes:

• Omitting default assignments
• Confusing clocked and combinational blocks
• Using incomplete else branches

3. Given the following Verilog code, what is the inferred hardware behavior?

always @(*) begin
  if (a) out = 1;
  else if (b) out = 0;
  // no assignment if neither a nor b
end

medium

A. Latch inferred to hold previous value when neither a nor b is true

B. Combinational logic with no latch

C. Synthesis error due to missing assignments

D. Flip-flop inferred with clock input

Solution

1. Step 1: Analyze assignment coverage

   The code assigns 'out' only when 'a' or 'b' is true; no assignment otherwise.

2. Step 2: Understand latch inference

   Missing assignment in some conditions causes Verilog to infer a latch to hold the last value.

3. Final Answer:

   Latch inferred to hold previous value when neither a nor b is true -> Option A

4. Quick Check:

   Missing else branch causes latch [OK]

Hint: Check if all conditions assign outputs; else latch inferred [OK]

Common Mistakes:

• Assuming no latch because of if-else
• Confusing latch with flip-flop
• Thinking synthesis error occurs

4. Identify the error in this Verilog code that causes latch inference:

always @(*) begin
  if (enable) out = data;
  // no else branch
end

How can it be fixed?

medium

A. Use non-blocking assignments instead of blocking

B. Change always @(*) to always @(posedge clk)

C. Add an else branch assigning a default value to 'out'

D. Remove the if condition entirely

Solution

1. Step 1: Identify missing assignment

   The code assigns 'out' only when 'enable' is true; no assignment otherwise causes latch.

2. Step 2: Fix by adding else branch

   Adding an else branch with a default assignment ensures 'out' is assigned in all cases, avoiding latch.

3. Final Answer:

   Add an else branch assigning a default value to 'out' -> Option C

4. Quick Check:

   Complete assignments prevent latch [OK]

Hint: Always include else branch or default assignment [OK]

Common Mistakes:

• Thinking clocked block fixes latch in combinational logic
• Ignoring missing else branch
• Confusing blocking and non-blocking assignments

5. You want to design a combinational logic block in Verilog that outputs 'result' based on inputs 'x' and 'y'. To avoid latch inference, which of the following coding styles is best?

always @(*) begin
  case ({x,y})
    2'b00: result = 0;
    2'b01: result = 1;
    2'b10: result = 1;
    // missing 2'b11 case
  endcase
end

hard

A. Use an always @(posedge clk) block instead

B. Add a default case assigning 'result' a value

C. Remove the case statement and use if-else only

D. Leave as is; synthesis tools will optimize automatically

Solution

1. Step 1: Identify incomplete case coverage

   The case statement misses the 2'b11 input combination, so 'result' is not assigned in that case.

2. Step 2: Add default case to assign 'result'

   Adding a default case ensures 'result' is assigned for all inputs, preventing latch inference.

3. Final Answer:

   Add a default case assigning 'result' a value -> Option B

4. Quick Check:

   Complete case coverage avoids latch [OK]

Hint: Always cover all cases or use default in case statements [OK]

Common Mistakes:

• Assuming missing case won't cause latch
• Switching to clocked block unnecessarily
• Ignoring default case importance