Latch inference and how to avoid it in Verilog - Interactive Code Practice

Practice - 5 Tasks

1fill in blank

easy

Complete the code to avoid latch inference by assigning a default value.

Verilog

always @(*) begin
  if (enable) begin
    out = in;
  end else begin
    out = [1];
  end
end

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A1'bz

B1'b0

Cenable

Din

Attempts:

3 left

💡 Hint

Common Mistakes

Not assigning 'out' in all branches causing latch inference.

Assigning 'out' only when 'enable' is true.

Assigning a default value like 1'b0 to 'out' in the else branch prevents latch inference by ensuring 'out' is always assigned.

2fill in blank

medium

Complete the sensitivity list to properly infer combinational logic.

Verilog

always @([1]) begin
  if (sel) out = a;
  else out = b;
end

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Aa or b

Bposedge clk

Cnegedge reset

D*

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock edges in combinational always blocks.

Listing only some inputs causing incomplete sensitivity.

Using '*' in the sensitivity list ensures the always block triggers on any input change, avoiding latch inference.

3fill in blank

hard

Fix the error in the code to avoid latch inference by completing the missing assignment.

Verilog

always @(*) begin
  case(sel)
    2'b00: out = a;
    2'b01: out = b;
    2'b10: out = c;
    // Missing default assignment
    [1]
  endcase
end

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Adefault: out = 1'b0;

Bdefault: out = out;

Cdefault: out = a;

Ddefault: out = 1'bz;

Attempts:

3 left

💡 Hint

Common Mistakes

Omitting the default case causing inferred latches.

Assigning 'out' to itself in default case which does not prevent latches.

Adding a default assignment ensures 'out' is assigned in all cases, preventing latch inference.

4fill in blank

hard

Fill both blanks to complete the code that avoids latch inference by assigning default values and using a complete sensitivity list.

Verilog

always @([1]) begin
  out = 1'b0; // default assignment
  if (enable) begin
    out = [2];
  end
end

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A*

Bin

Cenable

Dclk

Attempts:

3 left

💡 Hint

Common Mistakes

Using clock edges in combinational always blocks.

Not assigning default value before conditional assignment.

Using '*' ensures all inputs trigger the block, and assigning 'in' to 'out' when enabled avoids latch inference.

5fill in blank

hard

Fill both blanks to complete the code that avoids latch inference by assigning default values, using a complete sensitivity list, and including a default case.

Verilog

always @([1]) begin
  out = 1'b0; // default assignment
  case(sel)
    2'b00: out = a;
    2'b01: out = b;
    2'b10: out = c;
    [2]: out = 1'b0;
  endcase
end

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A*

Bdefault

C2'b11

Dposedge clk

Attempts:

3 left

💡 Hint

Common Mistakes

Omitting default case causing latch inference.

Using clock edge sensitivity in combinational block.

Using '*' sensitivity list covers all inputs, 'default' case handles unmatched cases, preventing latch inference.