Latch inference and how to avoid it in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output behavior of this Verilog code?

Consider the following Verilog code snippet:

module latch_example(input wire clk, input wire en, input wire d, output reg q);
  always @(posedge clk) begin
    if (en)
      q <= d;
  end
endmodule

What is the behavior of the output q?

Verilog

module latch_example(input wire clk, input wire en, input wire d, output reg q);
  always @(posedge clk) begin
    if (en)
      q <= d;
  end
endmodule

A q updates only on clock edge when en is high; no latch inferred.

B q holds previous value when en is low; latch inferred due to incomplete assignment.

C q updates asynchronously with d; latch inferred.

D q is always zero; no update occurs.

💡 Hint

Think about whether q is assigned in all cases inside the clocked block.

The code uses a clocked always block with a conditional assignment. Since q is assigned only when en is high, but the block is triggered only on clock edges, q holds its value otherwise naturally. This is a proper synchronous design and does not infer a latch.

❓ Predict Output

intermediate

What error does this Verilog code cause?

Examine this Verilog code:

module latch_infer(input wire a, b, output reg y);
  always @(*) begin
    if (a)
      y = b;
  end
endmodule

What happens when this code is synthesized?

Verilog

module latch_infer(input wire a, b, output reg y);
  always @(*) begin
    if (a)
      y = b;
  end
endmodule

A No latch inferred; y is combinational.

B A flip-flop is inferred because of the always @(*) block.

C Synthesis error due to missing else statement.

D A latch is inferred because y is not assigned in all paths.

💡 Hint

Check if y is assigned a value in every possible condition.

Since y is assigned only when a is true, but not assigned when a is false, the synthesizer infers a latch to hold the previous value of y. This is latch inference due to incomplete assignment in a combinational block.

🔧 Debug

advanced

Identify the latch inference in this code and fix it

Look at this Verilog code snippet:

module latch_bug(input wire a, b, output reg y);
  always @(*) begin
    if (a)
      y = b;
  end
endmodule

Which fix will prevent latch inference?

Verilog

module latch_bug(input wire a, b, output reg y);
  always @(*) begin
    if (a)
      y = b;
  end
endmodule

A Remove the if statement and assign y = b always;

B Change always @(*) to always @(posedge a);

C Add an else clause: else y = 1'b0;

D Declare y as wire instead of reg.

💡 Hint

Think about how to assign y in all cases inside the always block.

Adding an else clause ensures y is assigned in every possible path, preventing latch inference. Changing the sensitivity list or removing the if changes the design intent or causes errors. Declaring y as wire is invalid because y is assigned inside an always block.

🧠 Conceptual

advanced

Why does latch inference occur in combinational always blocks?

In Verilog, why does latch inference happen when using always @(*) blocks?

A Because <code>always @(*)</code> blocks are only for sequential logic and require flip-flops.

B Because the output variable is not assigned in all possible paths, so the synthesizer infers storage to hold the last value.

C Because the sensitivity list is incomplete, causing synthesis errors.

D Because the output variable is declared as wire instead of reg.

💡 Hint

Think about what happens if a variable is not assigned a value in every condition inside a combinational block.

Latches are inferred when a variable inside a combinational block is not assigned in all possible paths. The synthesizer infers storage (a latch) to hold the last value when no new assignment occurs. This is why complete assignments are necessary in combinational logic.

🚀 Application

expert

How to rewrite this code to avoid latch inference and keep intended behavior?

Given this Verilog code that infers a latch:

module latch_problem(input wire a, b, output reg y);
  always @(*) begin
    if (a)
      y = b;
  end
endmodule

Rewrite the always block to avoid latch inference but keep the same behavior: y should be b when a is true, and 0 otherwise.

A

always @(*) begin
  if (a)
    y = b;
  else
    y = 1'b0;
end

B

always @(posedge a) begin
  y <= b;
end

C assign y = a & b;

D always @(*) y = a ? b : 1'b0;

💡 Hint

Make sure y is assigned in all paths inside the always block.

Option A adds an else clause assigning y = 0 when a is false, preventing latch inference and preserving the intended behavior. Option A is a continuous assignment and cannot assign to reg y. Option A changes the design to sequential logic. Option A changes y to wire and changes the design style.