Latch inference and how to avoid it in Verilog - Practice Problems & Coding Challenges

Challenge - 5 Problems

❓ Predict Output

intermediate

What is the output behavior of this Verilog code?

Consider the following Verilog code snippet:

module latch_example(input wire clk, input wire en, input wire d, output reg q);
  always @(posedge clk) begin
    if (en)
      q <= d;
  end
endmodule

What is the behavior of the output q?

Verilog

module latch_example(input wire clk, input wire en, input wire d, output reg q);
  always @(posedge clk) begin
    if (en)
      q <= d;
  end
endmodule

A q updates only on clock edge when en is high; no latch inferred.

B q holds previous value when en is low; latch inferred due to incomplete assignment.

C q updates asynchronously with d; latch inferred.

D q is always zero; no update occurs.

💡 Hint

Think about whether q is assigned in all cases inside the clocked block.

The code uses a clocked always block with a conditional assignment. Since q is assigned only when en is high, but the block is triggered only on clock edges, q holds its value otherwise naturally. This is a proper synchronous design and does not infer a latch.

❓ Predict Output

intermediate

What error does this Verilog code cause?

Examine this Verilog code:

module latch_infer(input wire a, b, output reg y);
  always @(*) begin
    if (a)
      y = b;
  end
endmodule

What happens when this code is synthesized?

Verilog

module latch_infer(input wire a, b, output reg y);
  always @(*) begin
    if (a)
      y = b;
  end
endmodule

A No latch inferred; y is combinational.

B A flip-flop is inferred because of the always @(*) block.

C Synthesis error due to missing else statement.

D A latch is inferred because y is not assigned in all paths.

💡 Hint

Check if y is assigned a value in every possible condition.

Since y is assigned only when a is true, but not assigned when a is false, the synthesizer infers a latch to hold the previous value of y. This is latch inference due to incomplete assignment in a combinational block.

🔧 Debug

advanced

Identify the latch inference in this code and fix it

Look at this Verilog code snippet:

module latch_bug(input wire a, b, output reg y);
  always @(*) begin
    if (a)
      y = b;
  end
endmodule

Which fix will prevent latch inference?

Verilog

module latch_bug(input wire a, b, output reg y);
  always @(*) begin
    if (a)
      y = b;
  end
endmodule

A Remove the if statement and assign y = b always;

B Change always @(*) to always @(posedge a);

C Add an else clause: else y = 1'b0;

D Declare y as wire instead of reg.

💡 Hint

Think about how to assign y in all cases inside the always block.

Adding an else clause ensures y is assigned in every possible path, preventing latch inference. Changing the sensitivity list or removing the if changes the design intent or causes errors. Declaring y as wire is invalid because y is assigned inside an always block.

🧠 Conceptual

advanced

Why does latch inference occur in combinational always blocks?

In Verilog, why does latch inference happen when using always @(*) blocks?

A Because <code>always @(*)</code> blocks are only for sequential logic and require flip-flops.

B Because the output variable is not assigned in all possible paths, so the synthesizer infers storage to hold the last value.

C Because the sensitivity list is incomplete, causing synthesis errors.

D Because the output variable is declared as wire instead of reg.

💡 Hint

Think about what happens if a variable is not assigned a value in every condition inside a combinational block.

Latches are inferred when a variable inside a combinational block is not assigned in all possible paths. The synthesizer infers storage (a latch) to hold the last value when no new assignment occurs. This is why complete assignments are necessary in combinational logic.

🚀 Application

expert

How to rewrite this code to avoid latch inference and keep intended behavior?

Given this Verilog code that infers a latch:

module latch_problem(input wire a, b, output reg y);
  always @(*) begin
    if (a)
      y = b;
  end
endmodule

Rewrite the always block to avoid latch inference but keep the same behavior: y should be b when a is true, and 0 otherwise.

A

always @(*) begin
  if (a)
    y = b;
  else
    y = 1'b0;
end

B

always @(posedge a) begin
  y <= b;
end

C assign y = a & b;

D always @(*) y = a ? b : 1'b0;

💡 Hint

Make sure y is assigned in all paths inside the always block.

Option A adds an else clause assigning y = 0 when a is false, preventing latch inference and preserving the intended behavior. Option A is a continuous assignment and cannot assign to reg y. Option A changes the design to sequential logic. Option A changes y to wire and changes the design style.

Practice

1. What causes latch inference in Verilog combinational blocks?

easy

A. Assigning default values to outputs

B. Using clocked always blocks

C. Using non-blocking assignments

D. Not assigning output signals in all possible conditions

Solution

1. Step 1: Understand latch inference context

   Latch inference occurs when outputs inside combinational blocks are not assigned in every possible condition.

2. Step 2: Identify cause of latch inference

   If an output is missing assignment in some branches, Verilog infers a latch to hold the previous value.

3. Final Answer:

   Not assigning output signals in all possible conditions -> Option D

4. Quick Check:

   Missing assignments cause latch inference [OK]

Hint: Always assign outputs in every condition to avoid latches [OK]

Common Mistakes:

• Thinking clocked blocks cause latch inference
• Believing non-blocking assignments cause latches
• Ignoring missing else branches

2. Which Verilog code snippet correctly avoids latch inference in a combinational block?

easy

A. always @(*) begin
out = 0;
if (sel) out = 1;
end

B. always @(*) begin
if (sel) out = 1;
end

C. always @(posedge clk) begin
if (sel) out <= 1;
end

D. always @(*) begin
if (sel) out = 1;
else if (sel) out = 0;
end

Solution

1. Step 1: Check for default assignment

   always @(*) begin out = 0; if (sel) out = 1; end assigns a default value to 'out' before conditional checks, preventing latch inference.

2. Step 2: Compare other options

   always @(*) begin if (sel) out = 1; end misses assignment when 'sel' is false, causing latch. always @(posedge clk) begin if (sel) out <= 1; end is clocked, not combinational. always @(*) begin if (sel) out = 1; else if (sel) out = 0; end misses assignment when 'sel' is false since both conditions require sel true, causing latch.

3. Final Answer:

   Assigning default value before conditions to avoid latches -> Option A

4. Quick Check:

   Default assignment prevents latch [OK]

Hint: Assign default output values at start of combinational blocks [OK]

Common Mistakes:

• Omitting default assignments
• Confusing clocked and combinational blocks
• Using incomplete else branches

3. Given the following Verilog code, what is the inferred hardware behavior?

always @(*) begin
  if (a) out = 1;
  else if (b) out = 0;
  // no assignment if neither a nor b
end

medium

A. Latch inferred to hold previous value when neither a nor b is true

B. Combinational logic with no latch

C. Synthesis error due to missing assignments

D. Flip-flop inferred with clock input

Solution

1. Step 1: Analyze assignment coverage

   The code assigns 'out' only when 'a' or 'b' is true; no assignment otherwise.

2. Step 2: Understand latch inference

   Missing assignment in some conditions causes Verilog to infer a latch to hold the last value.

3. Final Answer:

   Latch inferred to hold previous value when neither a nor b is true -> Option A

4. Quick Check:

   Missing else branch causes latch [OK]

Hint: Check if all conditions assign outputs; else latch inferred [OK]

Common Mistakes:

• Assuming no latch because of if-else
• Confusing latch with flip-flop
• Thinking synthesis error occurs

4. Identify the error in this Verilog code that causes latch inference:

always @(*) begin
  if (enable) out = data;
  // no else branch
end

How can it be fixed?

medium

A. Use non-blocking assignments instead of blocking

B. Change always @(*) to always @(posedge clk)

C. Add an else branch assigning a default value to 'out'

D. Remove the if condition entirely

Solution

1. Step 1: Identify missing assignment

   The code assigns 'out' only when 'enable' is true; no assignment otherwise causes latch.

2. Step 2: Fix by adding else branch

   Adding an else branch with a default assignment ensures 'out' is assigned in all cases, avoiding latch.

3. Final Answer:

   Add an else branch assigning a default value to 'out' -> Option C

4. Quick Check:

   Complete assignments prevent latch [OK]

Hint: Always include else branch or default assignment [OK]

Common Mistakes:

• Thinking clocked block fixes latch in combinational logic
• Ignoring missing else branch
• Confusing blocking and non-blocking assignments

5. You want to design a combinational logic block in Verilog that outputs 'result' based on inputs 'x' and 'y'. To avoid latch inference, which of the following coding styles is best?

always @(*) begin
  case ({x,y})
    2'b00: result = 0;
    2'b01: result = 1;
    2'b10: result = 1;
    // missing 2'b11 case
  endcase
end

hard

A. Use an always @(posedge clk) block instead

B. Add a default case assigning 'result' a value

C. Remove the case statement and use if-else only

D. Leave as is; synthesis tools will optimize automatically

Solution

1. Step 1: Identify incomplete case coverage

   The case statement misses the 2'b11 input combination, so 'result' is not assigned in that case.

2. Step 2: Add default case to assign 'result'

   Adding a default case ensures 'result' is assigned for all inputs, preventing latch inference.

3. Final Answer:

   Add a default case assigning 'result' a value -> Option B

4. Quick Check:

   Complete case coverage avoids latch [OK]

Hint: Always cover all cases or use default in case statements [OK]

Common Mistakes:

• Assuming missing case won't cause latch
• Switching to clocked block unnecessarily
• Ignoring default case importance