Latch inference and how to avoid it in Verilog - Mini Project: Build & Apply

Latch inference and how to avoid it

📖 Scenario: Imagine you are designing a simple digital circuit that controls a light based on a switch. You want to make sure the circuit behaves predictably without unintended memory elements called latches.

🎯 Goal: You will write Verilog code step-by-step to create a combinational logic block that avoids latch inference by properly assigning outputs in all conditions.

📋 What You'll Learn

Create a Verilog module with an input switch and output light

Add a control variable enable to decide when the light should respond

Write combinational logic using an always @(*) block that assigns light based on switch and enable

Ensure light is assigned in all cases to avoid latch inference

Print the final Verilog code showing the correct latch-free logic

💡 Why This Matters

🌍 Real World

Latch inference can cause unexpected behavior in digital circuits, leading to bugs in hardware like FPGAs or ASICs. Avoiding latches is important for reliable electronics.

💼 Career

Hardware engineers and FPGA developers must understand latch inference to write clean, predictable Verilog code that synthesizes correctly and meets timing requirements.

1

Create the Verilog module with input and output

Write a Verilog module named LightControl with an input switch and an output light. Declare light as a reg type.

Verilog

module LightControl(input switch, output reg light);

// Your code here

endmodule

Need a hint?

Start by defining the module and its ports exactly as described.

2

Add an enable input to control the light

Add an input called enable to the LightControl module. This input will control when the light can turn on or off.

Verilog

module LightControl(input switch, input enable, output reg light);

// Your code here

endmodule

Need a hint?

Remember to add input enable inside the module port list.

3

Write combinational logic to assign light without latches

Inside the LightControl module, write an always @(*) block. Use an if statement to set light = switch when enable is 1. Otherwise, set light = 0. This ensures light is assigned in all cases and avoids latch inference.

Verilog

module LightControl(input switch, input enable, output reg light);

always @(*) begin
    // Your code here
end

endmodule

Need a hint?

Make sure to assign light in both the if and else parts.

4

Print the final Verilog code

Print the complete Verilog code of the LightControl module with the combinational logic that avoids latch inference.

Verilog

// Print the Verilog code below
// Your code here

Need a hint?

Print the entire module code exactly as written to show the final solution.